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AD6672 数据手册DataSheet下载
IF Receiver
AD6672
FUNCTIONAL BLOCK DIAGRAM
AVDD
VIN+
VIN–
PIPELINE
ADC
AGND
14
DRVDD
NOISE SHAPING
REQUANTIZER
VCM
AD6672
11
DCO±
REFERENCE
SDIO
D9±/D10±
OR±
1-TO-8
CLOCK
DIVIDER
SERIAL PORT
SCLK
0/D0±
CSB
CLK+
CLK–
09997-001
Performance with NSR enabled
SNR: 75.2 dBFS in a 55 MHz band to 185 MHz at 250 MSPS
SNR: 72.8 dBFS in an 82 MHz band to 185 MHz at 250 MSPS
Performance with NSR disabled
SNR: 66.4 dBFS up to 185 MHz at 250 MSPS
SFDR: 87 dBc up to 185 MHz at 250 MSPS
Total power consumption: 358 mW at 250 MSPS
1.8 V supply voltages
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Internal ADC voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
Differential analog inputs with 350 MHz bandwidth
Serial port control
Energy saving power-down modes
User-configurable, built-in self test (BIST) capability
DATA MULITIPLEXER
AND LVDS DRIVERS
FEATURES
Figure 1.
APPLICATIONS
Communications
Diversity radio and smart antenna (MIMO) systems
Multimode digital receivers (3G)
WCDMA, LTE, CDMA2000
WiMAX, TD-SCDMA
I/Q demodulation systems
General-purpose software radios
GENERAL DESCRIPTION
The AD6672 is an 11-bit intermediate receiver with sampling
speeds of up to 250 MSPS. The AD6672 is designed to support
communications applications, where low cost, small size, wide
bandwidth, and versatility are desired.
The ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations. A duty cycle stabilizer is provided
to compensate for variations in the ADC clock duty cycle,
allowing the converters to maintain excellent performance.
The ADC core output is connected internally to a noise shaping
requantizer (NSR) block. The device supports two output modes
that are selectable via the serial port interface (SPI). With the
NSR feature enabled, the outputs of the ADCs are processed such
that the AD6672 supports enhanced SNR performance within a
limited region of the Nyquist bandwidth while maintaining an
11-bit output resolution. The NSR block is programmed to provide
a bandwidth of up to 33% of the sample clock. For example, with
a sample clock rate of 250 MSPS, the AD6672 can achieve up to
73.6 dBFS SNR for an 82 MHz bandwidth at 185 MHz fIN.
With the NSR block disabled, the ADC data is provided directly
to the output with an output resolution of 11 bits. The AD6672
can achieve up to 66.6 dBFS SNR for the entire Nyquist bandwidth
when operated in this mode.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
www.BDTIC.com/ADI/
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
AD6672
TABLE OF CONTENTS
Features .............................................................................................. 1 Voltage Reference ....................................................................... 18 Applications....................................................................................... 1 Clock Input Considerations...................................................... 18 Functional Block Diagram .............................................................. 1 Power Dissipation and Standby Mode .................................... 19 General Description ......................................................................... 1 Digital Outputs ........................................................................... 20 Revision History ............................................................................... 2 ADC Overrange (OR)................................................................ 20 Product Highlights ........................................................................... 3 Noise Shaping Requantizer ........................................................... 21 Specifications..................................................................................... 4 22% BW NSR Mode (55 MHz BW at 250 MSPS) ..................... 21 ADC DC Specifications ............................................................... 4 33% BW NSR Mode (>82 MHz BW at 250 MSPS) ............... 21 ADC AC Specifications ............................................................... 5 Serial Port Interface (SPI).............................................................. 23 Digital Specifications ................................................................... 7 Configuration Using the SPI..................................................... 23 Switching Specifications .............................................................. 8 Hardware Interface..................................................................... 23 Timing Specifications .................................................................. 9 SPI Accessible Features.............................................................. 24 Absolute Maximum Ratings.......................................................... 10 Memory Map .................................................................................. 25 Thermal Characteristics ............................................................ 10 Reading the Memory Map Register Table............................... 25 ESD Caution................................................................................ 10 Memory Map Register Table..................................................... 26 Pin Configurations and Function Descriptions ......................... 11 Memory Map Register Description ......................................... 28 Typical Performance Characteristics ........................................... 12 Applications Information .............................................................. 29 Equivalent Circuits ......................................................................... 15 Design Guidelines ...................................................................... 29 Theory of Operation ...................................................................... 16 Outline Dimensions ....................................................................... 30 ADC Architecture ...................................................................... 16 Ordering Guide .......................................................................... 30 Analog Input Considerations.................................................... 16 REVISION HISTORY
7/11—Revision 0: Initial Version
www.BDTIC.com/ADI/
Rev. 0 | Page 2 of 32
AD6672
When the NSR block is disabled, the ADC data is provided directly
to the output at a resolution of 11 bits. This allows the AD6672
to be used in telecommunication applications, such as a digital
predistortion observation path, where wider bandwidths are
required.
PRODUCT HIGHLIGHTS
After digital signal processing, multiplexed output data is
routed into one 11-bit output port such that the maximum
data rate is 500 Mbps (DDR). This output is LVDS and
supports ANSI-644 levels.
3.
1.
2.
4.
The AD6672 receiver digitizes a wide spectrum of IF frequencies.
This IF sampling architecture greatly reduces component cost
and complexity compared with traditional analog techniques or
less integrated digital methods.
5.
Flexible power-down options allow significant power savings.
Programming for device setup and control is accomplished
using a 3-wire, SPI-compatible serial interface with numerous
modes to support board level system testing.
Integrated 11-bit, 250 MSPS ADC with a noise shaping
requantizer option.
Operation from a single 1.8 V supply and a separate digital
output driver supply accommodating LVDS outputs.
On-chip 1-to-8 integer clock divider function to support a
wide range of clocking.
Noise shaping requantizer function allows attaining improved
SNR within a reduced frequency band. With NSR enabled,
the AD6672 supports up to 82 MHz at 250 MSPS.
Standard serial port interface (SPI) that supports various
product features and functions, such as data formatting
(offset binary, twos complement, or gray coding), enabling
the clock DCS, power-down, test modes, and voltage
reference mode.
The AD6672 is available in a 32-lead, RoHS-compliant LFCSP
and is specified over the industrial temperature range of −40°C
to +85°C. This product is protected by a U.S. patent.
www.BDTIC.com/ADI/
Rev. 0 | Page 3 of 32
AD6672
SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range,
DCS enabled, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL) 1
TEMPERATURE DRIFT
Offset Error
Gain Error
INPUT-REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span
Input Capacitance 2
Input Resistance
Input Common-Mode Voltage
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD1
IDRVDD1 (NSR Disabled)
IDRVDD1 (NSR Enabled, 22% Bandwidth Mode)
IDRVDD1 (NSR Enabled, 33% Bandwidth Mode)
POWER CONSUMPTION
Sine Wave Input (DRVDD = 1.8 V, NSR Disabled)
Sine Wave Input (DRVDD = 1.8 V, NSR Enabled,
22% Bandwidth Mode)
Sine Wave Input (DRVDD = 1.8 V, NSR Enabled,
33% Bandwidth Mode)
Standby Power 3
Power-Down Power
Temperature
Full
Min
11
Max
Unit
Bits
±11
+3/−6.5
±0.2
±0.12
mV
% FSR
LSB
LSB
LSB
LSB
Full
Full
±7
±85
ppm/°C
ppm/°C
25°C
0.65
LSB rms
Full
Full
Full
Full
1.75
5
20
0.9
V p-p
pF
kΩ
V
Full
Full
Full
Full
25°C
Full
25°C
Full
Full
Typ
Guaranteed
±0.1
±0.3
1.7
1.7
1.8
1.8
1.9
1.9
V
V
Full
Full
Full
Full
136
63
89
99
145
68
mA
mA
mA
mA
Full
358
385
mW
mW
Full
405
Full
Full
Full
423
50
5
mW
1
mW
mW
Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 18 for the equivalent analog input structure.
3
Standby power is measured with a dc input, the CLK pin inactive (set to AVDD or AGND).
2
www.BDTIC.com/ADI/
Rev. 0 | Page 4 of 32
AD6672
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, unless
otherwise noted.
Table 2.
Parameter 1
SIGNAL-TO-NOISE-RATIO (SNR)
NSR Disabled
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
NSR Enabled
22% Bandwidth Mode
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
33% Bandwidth Mode
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
SIGNAL-TO-NOISE RATIO AND DISTORTION (SINAD)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
Temperature
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
Min
Typ
Max
66.6
66.6
66.5
66.4
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
65.4
66.3
75.8
75.7
75.6
75.2
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
72.2
74.8
73.4
73.3
73.2
72.8
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
69.2
72.4
65.7
65.7
65.6
65.3
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
64.4
65.2
25°C
25°C
25°C
25°C
Full
25°C
−88
−88
−89
−87
25°C
25°C
25°C
25°C
Full
25°C
88
88
89
87
−80
−88
80
88
www.BDTIC.com/ADI/
Rev. 0 | Page 5 of 32
Unit
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
AD6672
Parameter 1
WORST OTHER (HARMONIC OR SPUR)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
TWO-TONE SFDR
fIN = 184.12 MHz, 187.12 MHz (−7 dBFS)
FULL POWER BANDWIDTH 2
NOISE BANDWIDTH 3
Temperature
Min
Typ
Max
Unit
25°C
25°C
25°C
25°C
Full
25°C
−96
−97
−97
−98
−97
dBc
dBc
dBc
dBc
dBc
dBc
25°C
25°C
25°C
88
350
1000
dBc
MHz
MHz
−81
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Full power bandwidth is the bandwidth of operation where typical ADC performance can be achieved.
3
Noise bandwidth is the −3 dB bandwidth for the ADC inputs across which noise may enter the ADC and is not attenuated internally.
2
www.BDTIC.com/ADI/
Rev. 0 | Page 6 of 32
AD6672
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,
DCS enabled, unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
LOGIC INPUT (CSB) 1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT (SCLK) 2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (SDIO)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
DIGITAL OUTPUTS (OR+, OR−)
LVDS Data and OR Outputs
Differential Output Voltage (VOD), ANSI Mode
Output Offset Voltage (VOS), ANSI Mode
Differential Output Voltage (VOD), Reduced Swing Mode
Output Offset Voltage (VOS), Reduced Swing Mode
1
2
Temperature
Min
Full
Full
Full
Full
Full
Full
Full
Full
CMOS/LVDS/LVPECL
0.9
0.3
3.6
AGND
AVDD
0.9
1.4
10
+22
−22
−10
4
12
15
18
Full
Full
Full
Full
Full
Full
1.22
0
50
−5
Full
Full
Full
Full
Full
Full
1.22
0
45
−5
Full
Full
Full
Full
Full
Full
1.22
0
45
−5
Full
Full
Full
Full
250
1.15
150
1.15
Typ
2.1
0.6
70
+5
V
V
μA
μA
kΩ
pF
2.1
0.6
70
+5
V
V
μA
μA
kΩ
pF
450
1.35
280
1.35
mV
V
mV
V
26
5
www.BDTIC.com/ADI/
V
V p-p
V
V
μA
μA
pF
kΩ
V
V
μA
μA
kΩ
pF
26
2
350
1.25
200
1.25
Unit
2.1
0.6
71
+5
26
2
Pull-up.
Pull-down.
Rev. 0 | Page 7 of 32
Max
AD6672
SWITCHING SPECIFICATIONS
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate 1
CLK Period—Divide-by-1 Mode (tCLK)
CLK Pulse Width High (tCH)
Divide-by-1 Mode, DCS Enabled
Divide-by-1 Mode, DCS Disabled
Divide-by-2 Mode Through Divide-by-8 Mode
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
DATA OUTPUT PARAMETERS
Data Propagation Delay (tPD)
DCO Propagation Delay (tDCO)
DCO-to-Data Skew (tSKEW)
Pipeline Delay (Latency)—NSR Disabled
Pipeline Delay (Latency)—NSR Enabled
Wake-Up Time (from Standby)
Wake-Up Time (from Power-Down)
Out-of-Range Recovery Time
1
Temperature
Min
Full
Full
Full
40
4
Full
Full
Full
Full
Full
1.8
1.9
0.8
Full
Full
Full
Full
Full
Full
Full
Full
4.1
4.7
0.3
Typ
2.0
2.0
Max
Unit
625
250
MHz
MSPS
ns
2.2
2.1
ns
ns
ns
ns
ps rms
5.2
5.8
0.7
ns
ns
ns
Cycles
Cycles
μs
μs
Cycles
1.0
0.1
4.7
5.3
0.5
10
13
10
100
3
Conversion rate is the clock rate after the divider.
Timing Diagram
tA
N+4
N–1
VIN
N+5
N
N+3
N+1
tCH
N+2
tCLK
CLK+
CLK–
tDCO
DCO–
DCO+
tSKEW
tPD
0/D0±
(LSB)
0
N – 10
D0
N – 10
0
N–9
D0
N–9
0
N–8
D0
N–8
0
N–7
D0
N–7
0
N–6
D9±/D10±
(MSB)
D9
N – 10
D10
N – 10
D9
N–9
D10
N–9
D9
N–8
D10
N–8
D9
N–7
D10
N–7
D9
N–6
Figure 2. LVDS Data Output Timing
www.BDTIC.com/ADI/
Rev. 0 | Page 8 of 32
09997-002
ODD/EVEN
AD6672
TIMING SPECIFICATIONS
Table 5.
Parameter
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
tDIS_SDIO
Test Conditions/Comments
See Figure 42 for the SPI timing diagram
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Time required for the SDIO pin to switch from an input to an output
relative to the SCLK falling edge (not shown in Figure 42)
Time required for the SDIO pin to switch from an output to an input
relative to the SCLK rising edge (not shown in Figure 42)
Min
Max
Unit
2
2
40
2
2
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
10
ns
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Rev. 0 | Page 9 of 32
Typ
AD6672
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
Electrical
AVDD to AGND
DRVDD to AGND
VIN+, VIN− to AGND
CLK+, CLK− to AGND
VCM to AGND
CSB to AGND
SCLK to AGND
SDIO to AGND
0/D0−, 0/D0 + Through D9−/D10−,
D9+/D10+ to AGND
OR+/OR− to AGND
DCO+, DCO− to AGND
Environmental
Operating Temperature Range
(Ambient)
Maximum Junction Temperature
Under Bias
Storage Temperature Range
(Ambient)
THERMAL CHARACTERISTICS
Rating
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
The exposed paddle must be soldered to the ground plane for the
LFCSP package. Soldering the exposed paddle to the customer
board increases the reliability of the solder joints, maximizing
the thermal capability of the package.
Table 7. Thermal Resistance
Package
Type
32-Lead LFCSP
5 mm × 5 mm
(CP-32-12)
Airflow
Velocity
(m/sec)
0
1.0
2.0
θJA1, 2
37.1
32.4
29.1
θJC1, 3
3.1
θJB1, 4
20.7
Unit
°C/W
°C/W
°C/W
1
Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3
Per MIL-Std 883, Method 1012.1.
4
Per JEDEC JESD51-8 (still air).
2
−40°C to +85°C
150°C
−65°C to +125°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Typical θJA is specified for a 4-layer PCB with a solid ground
plane. As shown in Table 7, airflow increases heat dissipation,
which reduces θJA. In addition, metal in direct contact with the
package leads from metal traces—through holes, ground, and
power planes—reduces the θJA.
ESD CAUTION
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Rev. 0 | Page 10 of 32
AD6672
32
31
30
29
28
27
26
25
AVDD
AVDD
VIN+
VIN–
AVDD
AVDD
VCM
DNC
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
AD6672
INTERLEAVED
LVDS
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
CSB
SCLK
SDIO
DCO+
DCO–
D9+/D10+ (MSB)
D9–/D10– (MSB)
DRVDD
D1–/D2–
D1+/D2+
D3–/D4–
D3+/D4+
D5–/D6–
D5+/D6+
D7–/D8–
D7+/D8+
9
10
11
12
13
14
15
16
CLK+
CLK–
AVDD
OR–
OR+
0/D0– (LSB)
0/D0+ (LSB)
DRVDD
09997-003
NOTES
1. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE
PACKAGE PROVIDES THE ANALOG GROUND FOR THE
PART. THIS EXPOSED PADDLE MUST BE CONNECTED TO
GROUND FOR PROPER OPERATION.
2. DNC = NO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
Figure 3. LFCSP Pin Configuration (Top View)
Table 8. Pin Function Descriptions
Pin No.
ADC Power Supplies
8, 17
3, 27, 28, 31, 32
0
25
ADC Analog
30
29
26
1
2
Digital Outputs
5
4
7
6
10
9
12
11
14
13
16
15
19
18
21
20
SPI Control
23
22
24
Mnemonic
Type
Description
DRVDD
AVDD
AGND,
Exposed Paddle
Supply
Supply
Ground
Digital Output Driver Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
Analog Ground. The exposed thermal paddle on the bottom of the package provides the
analog ground for the part. This exposed paddle must be connected to ground for proper
operation.
Do Not Connect. Do not connect to this pin.
VIN+
VIN−
VCM
Input
Input
Output
CLK+
CLK−
Input
Input
Differential Analog Input Pin (+).
Differential Analog Input Pin (−).
Common-Mode Level Bias Output for Analog Inputs. This pin should be decoupled to
ground using a 0.1 μF capacitor.
ADC Clock Input—True.
ADC Clock Input—Complement.
OR+
OR−
0/D0+ (LSB)
Output
Output
Output
0/D0− (LSB)
Output
D1+/D2+
D1−/D2−
D3+/D4+
D3−/D4−
D5+/D6+
D5−/D6−
D7+/D8+
D7−/D8−
D9+/D10+ (MSB)
D9−/D10− (MSB)
DCO+
DCO−
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Overrange indicator—True.
Overrange indicator—Complement.
DDR LVDS Output Data 0—True. The output bit on the rising edge of the data clock output
(DCO) from this output is always a Logic 0 (see Figure 2).
DDR LVDS Output Data 0—Complement. The output bit on the rising edge of the data clock
output (DCO) from this output is always a Logic 0 (see Figure 2).
DDR LVDS Output Data 1/2—True.
DDR LVDS Output Data 1/2—Complement.
DDR LVDS Output Data 3/4—True.
DDR LVDS Output Data 3/4—Complement.
DDR LVDS Output Data 5/6—True.
DDR LVDS Output Data 5/6—Complement.
DDR LVDS Output Data 7/8—True.
DDR LVDS Output Data 7/8—Complement.
DDR LVDS Output Data 9/10—True.
DDR LVDS Output Data 9/10—Complement.
LVDS Data Clock Output—True.
LVDS Data Clock Output—Complement.
SCLK
SDIO
CSB
Input
Input/output
Input
SPI Serial Clock.
SPI Serial Data I/O.
SPI Chip Select (Active Low).
DNC
www.BDTIC.com/ADI/
Rev. 0 | Page 11 of 32
AD6672
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = 250 MSPS, DCS enabled, 1.75 V p-p differential input, VIN = −1.0 dBFS, 32k sample, TA = 25°C,
unless otherwise noted.
0
–20
–40
–60
SECOND
HARMONIC
250 MSPS
185.1MHz @ –1.0dBFS
SNR = 65.4dB (66.4dBFS)
SFDR = 87dBc
–20
AMPLITUDE (dBFS)
THIRD
HARMONIC
–80
–100
–120
–40
–60
THIRD
HARMONIC
–100
10
20
30
40
50
60
70
80
90
100 110 120
FREQUENCY (MHz)
–140
09997-004
0
0
50
60
70
80
90
100 110 120
250 MSPS
220.1MHz @ –1.0dBFS
SNR = 65.3dB (66.3dBFS)
SFDR = 88dBc
–20
AMPLITUDE (dBFS)
–60
SECOND
HARMONIC
–80
–100
–120
–40
–60
SECOND
HARMONIC
THIRD
HARMONIC
–80
–100
–120
0
10
20
30
40
50
60
70
80
90
100 110 120
FREQUENCY (MHz)
–140
09997-005
–140
0
30
40
50
60
0
80
90
100 110 120
250 MSPS
305.1MHz @ –1.0dBFS
SNR = 64.8dB (65.8dBFS)
SFDR = 82dBc
–20
AMPLITUDE (dBFS)
–40
–60
SECOND
HARMONIC
70
Figure 8. Single-Tone FFT with fIN = 220.1 MHz
250MSPS
140.1MHz @ –1.0dBFS
SNR = 65.5dB (66.5dBFS)
SFDR = 89dBc
–20
20
FREQUENCY (MHz)
Figure 5. Single-Tone FFT with fIN = 90.1 MHz
0
10
09997-008
AMPLITUDE (dBFS)
40
0
–40
THIRD
HARMONIC
30
Figure 7. Single-Tone FFT with fIN = 185.1 MHz
250MSPS
90.1MHz @ –1.0dBFS
SNR = 65.6dB (66.6dBFS)
SFDR = 88dBc
–20
20
FREQUENCY (MHz)
Figure 4. Single-Tone FFT with fIN = 30.1 MHz
0
10
09997-007
–120
–140
THIRD
HARMONIC
–80
–100
–120
–40
–60
THIRD
HARMONIC
SECOND
HARMONIC
–80
–100
–120
–140
0
10
20
30
40
50
60
70
80
90
100 110 120
FREQUENCY (MHz)
09997-006
AMPLITUDE (dBFS)
SECOND
HARMONIC
–80
Figure 6. Single-Tone FFT with fIN = 140.1 MHz
–140
0
10
20
30
40
50
60
70
80
90
100 110 120
FREQUENCY (MHz)
Figure 9. Single-Tone FFT with fIN = 305.1 MHz
www.BDTIC.com/ADI/
Rev. 0 | Page 12 of 32
09997-009
AMPLITUDE (dBFS)
0
250MSPS
30.1MHz @ –1.0dBFS
SNR = 65.6dB (66.6dBFS)
SFDR = 88dBc
120
0
–20
SFDR (dBFS)
80
SNR (dBFS)
60
40
SFDR (dBc)
SNR (dBc)
20
–40
–60
–80
SFDR (dBFS)
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
INPUT AMPLITUDE (dBFS)
IMD3 (dBFS)
–120
–90.0
09997-010
0
–100
–78.5
–67.0
–55.5
–44.0
–32.5
–21.0
–9.5
INPUT AMPLITUDE (dBFS)
Figure 10. Single-Tone SNR/SFDR vs. Input Amplitude (AIN)
with fIN = 90.1 MHz, fS = 250 MSPS
Figure 13. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)
with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz, fS = 250 MSPS
100
0
95
250MSPS
89.12MHz @ –7.0dBFS
92.12MHz @ –7.0dBFS
SFDR = 87dBc (94dBFS)
–20
SFDR (dBFS)
90
AMPLITUDE (dBFS)
SNR/SFDR (dBc and dBFS)
SFDR (dBc)
IMD3 (dBc)
09997-013
SFDR/IMD3 (dBc and dBFS)
SNR/SFDR (dBc and dBFS)
100
85
80
75
70
–40
–60
–80
–100
FREQUENCY (MHz)
09997-011
330
345
315
300
285
255
270
240
195
210
225
180
165
150
135
120
90
–140
105
60
0
40
50
60
70
80
90
100 110 120
0
250MSPS
184.12MHz @ –7.0dBFS
187.12MHz @ –7.0dBFS
SFDR = 86dBc (93dBFS)
–20
–20
AMPLITUDE (dBFS)
SFDR (dBc)
IMD3 (dBc)
–60
–80
SFDR (dBFS)
–100
–80
–70
–60
–50
–40
–40
–60
–80
–100
–120
IMD3 (dBFS)
–30
–20
–10
INPUT AMPLITUDE (dBFS)
Figure 12. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)
with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz, fS = 250 MSPS
09997-012
SFDR/IMD3 (dBc and dBFS)
30
Figure 14. Two-Tone FFT with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz
0
–120
–90
20
FREQUENCY (Hz)
Figure 11. Single-Tone SNR/SFDR vs. Input Frequency (fIN), fS = 250 MSPS
–40
10
–140
0
10
20
30
40
50
60
70
80
90
100 110 120
FREQUENCY (Hz)
Figure 15. Two-Tone FFT with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz
www.BDTIC.com/ADI/
09997-015
75
–120
60
65
09997-014
SNR (dBc)
AD6672
100
1000
SFDR (dBc)
95
9000
0.65LSB RMS
16384 TOTAL HITS
NUMBER OF HITS
85
80
75
70
SNR (dBFS)
6000
5000
4000
3000
2000
65
1000
60
80
100
120
140
160
180
SAMPLE RATE (MSPS)
200
220
240
09997-016
60
40
7000
Figure 16. Single-Tone SNR/SFDR vs. Sample Rate (fS) with fIN = 90 MHz
0
N
N–1
OUTPUT CODE
Figure 17. Grounded Input Histogram, fS = 250 MSPS
www.BDTIC.com/ADI/
Rev. 0 | Page 14 of 32
09997-017
SNR/SFDR (dBc and dBFS)
8000
90
AD6672
EQUIVALENT CIRCUITS
DRVDD
AVDD
VIN
350Ω
SDIO
09997-021
09997-018
26kΩ
Figure 21. Equivalent SDIO Circuit
Figure 18. Equivalent Analog Input Circuit
AVDD
AVDD
AVDD
0.9V
26kΩ
CLK–
09997-019
CLK+
350Ω
SCLK
15kΩ
09997-022
15kΩ
Figure 19. Equivalent Clock Input Circuit
Figure 22. Equivalent SCLK Input Circuit
DRVDD
AVDD
26kΩ
V+
DATAOUT–
CSB
350Ω
DATAOUT+
V+
09997-023
09997-020
V–
V–
Figure 20. Equivalent LVDS Output Circuit
Figure 23. Equivalent CSB Input Circuit
www.BDTIC.com/ADI/
Rev. 0 | Page 15 of 32
AD6672
THEORY OF OPERATION
Programming and control of the AD6672 are accomplished
using a 3-pin, SPI-compatible serial interface.
ADC ARCHITECTURE
The AD6672 architecture consists of a front-end sample-andhold circuit, followed by a pipelined switched-capacitor ADC.
The quantized outputs from each stage are combined into a
final 11-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate on a new input
sample and the remaining stages to operate on the preceding
samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor digitalto-analog converter (DAC) and an interstage residue amplifier
(MDAC). The MDAC magnifies the difference between the
reconstructed DAC output and the flash input for the next stage
in the pipeline. One bit of redundancy is used in each stage to
facilitate digital correction of flash errors. The last stage simply
consists of a flash ADC.
The input stage of the AD6672 contains a differential sampling
circuit that can be ac- or dc-coupled in differential or singleended modes. The output staging block aligns the data, corrects
errors, and passes the data to the output buffers. The output
buffers are powered from a separate supply, allowing digital
output noise to be separated from the analog core. During
power-down, the output buffers go into a high impedance state.
The AD6672 features a noise shaping requantizer (NSR) to
allow higher than 11-bit SNR to be maintained in a subset of
the Nyquist band.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD6672 is a differential switchedcapacitor circuit that has been designed to attain optimum
performance when processing a differential input signal.
The clock signal alternatively switches the input between
sample mode and hold mode (see the configuration shown in
Figure 24). When the input is switched into sample mode, the
signal source must be capable of charging the sampling
capacitors and settling within 1/2 clock cycle.
A small resistor in series with each input can help reduce the
peak transient current required from the output stage of the
driving source. A shunt capacitor can be placed across the
inputs to provide dynamic charging currents. This passive
network creates a low-pass filter at the ADC input; therefore,
the precise values are dependent on the application.
In intermediate frequency (IF) undersampling applications, the
shunt capacitors should be reduced. In combination with the
driving source impedance, the shunt capacitors limit the input
bandwidth. Refer to the AN-742 Application Note, Frequency
Domain Response of Switched-Capacitor ADCs; the AN-827
Application Note, A Resonant Approach to Interfacing Amplifiers
to Switched-Capacitor ADCs; and the Analog Dialogue article,
“Transformer-Coupled Front-End for Wideband A/D Converters,”
for more information on this subject.
BIAS
S
S
CFB
CS
VIN+
CPAR1
CPAR2
H
S
S
CS
VIN–
CPAR1
CPAR2
S
S
BIAS
CFB
09997-024
The AD6672 can sample any fS/2 frequency segment from dc to
250 MHz using appropriate low-pass or band-pass filtering at
the ADC inputs with little loss in ADC performance.
Figure 24. Switched-Capacitor Input
For best dynamic performance, match the source impedances
driving VIN+ and VIN− and differentially balance the inputs.
Input Common Mode
The analog inputs of the AD6672 are not internally dc biased.
In ac-coupled applications, the user must provide this bias
externally. Setting the device so that VCM = 0.5 × AVDD (or
0.9 V) is recommended for optimum performance. An onboard common-mode voltage reference is included in the
design and is available from the VCM pin. Using the VCM
output to set the input common mode is recommended.
Optimum performance is achieved when the common-mode
voltage of the analog input is set by the VCM pin voltage
(typically 0.5 × AVDD). The VCM pin must be decoupled to
ground by a 0.1 μF capacitor, as described in the Applications
Information section. Place this decoupling capacitor close to the
pin to minimize the series resistance and inductance between
the part and this capacitor.
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Rev. 0 | Page 16 of 32
AD6672
Differential Input Configurations
the true SNR performance of the AD6672. For applications where
SNR is a key parameter, differential double balun coupling is
the recommended input configuration (see Figure 28). In this
configuration, the input is ac-coupled and the VCM voltage is
provided to the input through a 33 Ω resistor. This resistor
compensates for losses in the input baluns to provide a 50 Ω
impedance to the driver.
Optimum performance can be achieved when driving the AD6672
in a differential input configuration. For baseband applications, the
AD8138, ADA4937-1, and ADA4930-1 differential drivers provide
excellent performance and a flexible interface to the ADC.
The output common-mode voltage of the ADA4930-1 is easily
set with the VCM pin of the AD6672 (see Figure 25), and the
driver can be configured in a Sallen-Key filter topology to
provide band-limiting of the input signal.
In the double balun and transformer configurations, the value
of the input capacitors and resistors is dependent on the input
frequency and source impedance. Based on these parameters,
the value of the input resistors and capacitors may need to be
adjusted or some components may need to be removed. Table 9
displays recommended values to set the RC network for
different input frequency ranges. However, these values are
dependent on the input signal and bandwidth and should be
used only as a starting guide. Note that the values given in Table 9
are for each R1, R2, C2, and R3 component shown in Figure 26
and Figure 28.
15pF
200Ω
15Ω
VIN–
AVDD
5pF
ADC
ADA4930-1
0.1µF
33Ω
15Ω
120Ω
VCM
VIN+
200Ω
09997-025
15pF
0.1µF
Table 9. Example RC Network
Frequency
Range
(MHz)
0 to 100
100 to 300
Figure 25. Differential Input Configuration Using the ADA4930-1
For baseband applications where SNR is a key parameter,
differential transformer coupling is the recommended input
configuration. An example is shown in Figure 26. To bias the
analog input, connect the VCM voltage to the center tap of the
secondary winding of the transformer.
R2
VIN+
R1
49.9Ω
ADC
C1
R2
R1
R3
0.1µF
VCM
VIN–
1000pF
0.1µF
C2
R2
Series
(Ω)
0
0
301Ω
5.1pF
1nF
1µH
The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies
below a few megahertz. Excessive signal power can also cause
core saturation, which leads to distortion.
165Ω
VPOS
AD8375
Figure 26. Differential Transformer-Coupled Configuration
3.9pF
165Ω
R3
R1
0.1µF
S
S
P
0.1µF
AD6672
2.5kΩ║2pF
68nH
Figure 27. Differential Input Configuration Using the AD8375
R2
VIN+
33Ω
PA
15pF
VCM
1nF
C2
2V p-p
R3
Shunt
(Ω)
49.9
49.9
1000pF 180nH 220nH
NOTES
1. ALL INDUCTORS ARE COILCRAFT® 0603CS COMPONENTS
WITH THE EXCEPTION OF THE 1µH CHOKE INDUCTORS (0603LS).
2. FILTER VALUES SHOWN ARE FOR A 20MHz BANDWIDTH FILTER
CENTERED AT 140MHz.
At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
0.1µF
C2
Shunt
(pF)
15
8.2
180nH 220nH
1µH
09997-026
2V p-p
C1
Differential
(pF)
8.2
3.9
An alternative to using a transformer-coupled input at
frequencies in the second Nyquist zone is to use an amplifier
with variable gain. The AD8375 digital variable gain amplifier
(DVGA) provides good performance for driving the AD6672.
Figure 27 shows an example of the AD8375 driving the AD6672
through a band-pass antialiasing filter.
C2
R3
R1
Series
(Ω)
33
15
33Ω
0.1µF
C1
R1
ADC
R2
R3
C2
VIN–
VCM
0.1µF
www.BDTIC.com/ADI/
Figure 28. Differential Double Balun Input Configuration
Rev. 0 | Page 17 of 32
09997-027
33Ω
90Ω
09997-028
76.8Ω
VIN
AD6672
VOLTAGE REFERENCE
CLOCK
INPUT
25Ω
390pF
CLK+
390pF
1nF
CLK–
CLOCK INPUT CONSIDERATIONS
0.9V
Figure 31. Balun-Coupled Differential Clock (Up to 625 MHz)
If a low jitter clock source is not available, another option is to
ac-couple a differential PECL signal to the sample clock input
pins as shown in Figure 32. The AD9510, AD9511, AD9512,
AD9513, AD9514, AD9515, AD9516, AD9517, AD9518, AD9520,
AD9522, AD9523, AD9524, and ADCLK905/ADCLK907/
ADCLK925 clock drivers offer excellent jitter performance.
CLK+
AD95xx,
ADCLK9xx
CLK–
CLOCK
INPUT
09997-029
4pF
Clock Input Options
The AD6672 has a very flexible clock input structure. Clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter
is of the most concern, as described in the Jitter Considerations
section.
CLK–
50kΩ
240Ω
50kΩ
240Ω
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 33. The AD9510,
AD9511, AD9512, AD9513, AD9514, AD9515, AD9516,
AD9517, AD9518, AD9520, AD9522, AD9523, and AD9524
clock drivers offer excellent jitter performance.
0.1µF
0.1µF
AD95xx
CLOCK
INPUT
LVDS DRIVER
100Ω
0.1µF
CLK–
50kΩ
50kΩ
Figure 33. Differential LVDS Sample Clock (Up to 625 MHz)
Input Clock Divider
The AD6672 contains an input clock divider with the ability to
divide the input clock by integer values between 1 and 8. For
divide ratios other than 1, the duty cycle stabilizer (DCS) is
enabled by default on power-up.
ADC
CLK+
100Ω
390pF
09997-043
CLK–
SCHOTTKY
DIODES:
HSMS2822
ADC
CLK+
0.1µF
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 625 MHz, and the RF transformer is recommended for clock frequencies from 10 MHz to 250 MHz. The
back-to-back Schottky diodes across the secondary winding of
the transformer limit clock excursions into the AD6672 to
approximately 0.8 V p-p differential. This limit helps prevent
the large voltage swings of the clock from feeding through to
other portions of the AD6672 while preserving the fast rise and
fall times of the signal, which are critical for low jitter
performance.
50Ω
100Ω
0.1µF
CLOCK
INPUT
Figure 30 and Figure 31 show two preferable methods for
clocking the AD6672 (at clock rates of up to 625 MHz). A low
jitter clock source is converted from a single-ended signal to a
differential signal using an RF balun or RF transformer.
390pF
0.1µF PECL DRIVER
Figure 32. Differential PECL Sample Clock (Up to 625 MHz)
Figure 29. Simplified Equivalent Clock Input Circuit
Mini-Circuits®
ADT1-1WT, 1:1Z
390pF
XFMR
ADC
0.1µF
Figure 30. Transformer-Coupled Differential Clock (Up to 250 MHz)
www.BDTIC.com/ADI/
Rev. 0 | Page 18 of 32
09997-033
CLK+
CLOCK
INPUT
0.1µF
CLOCK
INPUT
09997-032
AVDD
4pF
SCHOTTKY
DIODES:
HSMS2822
25Ω
For optimum performance, the AD6672 sample clock inputs,
CLK+ and CLK−, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or via capacitors. These pins are biased
internally (see Figure 29) and require no external bias. If the
inputs are floated, the CLK− pin is pulled low to prevent
spurious clocking.
ADC
390pF
09997-044
A stable and accurate voltage reference is built into the AD6672.
The full-scale input range can be adjusted by varying the
reference voltage via SPI. The input span of the ADC tracks
reference voltage changes linearly.
AD6672
Jitter on the rising edge of the input clock is still of paramount
concern and is not reduced by the duty cycle stabilizer. The
duty cycle control loop does not function for clock rates less
than 40 MHz nominally. The loop has a time constant
associated with it that must be considered when the clock rate
may change dynamically. A wait time of 1.5 μs to 5 μs is
required after a dynamic clock frequency increase or decrease
before the DCS loop is relocked to the input signal. During the
time that the loop is not locked, the DCS loop is bypassed, and
internal device timing is dependent on the duty cycle of the
input clock signal. In such applications, it may be appropriate to
disable the duty cycle stabilizer. In all other applications,
enabling the DCS circuit is recommended to maximize ac
performance.
Jitter Considerations
Refer to the AN-501 Application Note, Aperture Uncertainty and
ADC System Performance, and the AN-756 Application Note,
Sampled Systems and the Effects of Clock Phase Noise and Jitter, for
more information about jitter performance as it relates to ADCs.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 35, the power dissipated by the AD6672 is
proportional to its sample rate. The data in Figure 35 was taken
using the same operating conditions as those used for the
Typical Performance Characteristics section.
0.40
0.20
0.30
SNRHF = −10 log[(2π × fIN × tJRMS) + 10
( − SNRLF /10)
65
60
55
50
1
10
100
INPUT FREQUENCY (MHz)
Figure 34. SNR vs. Input Frequency and Jitter
0.10
0.05
IDRVDD
55
70
0
85 100 115 130 145 160 175 190 205 220 235 250
Figure 35. AD6672-250 Power and Current vs. Sample Rate
By setting the internal power-down mode bits (Bits[1:0]) in the
power modes register (Address 0x08) to 01, the AD6672 is
placed in power-down mode. In this state, the ADC typically
dissipates 2.5 mW. During power-down, the output drivers are
placed in a high impedance state.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering
power-down mode and then must be recharged when returning
to normal operation. As a result, the wake-up time is related to
the time spent in power-down mode, and shorter power-down
cycles result in proportionally shorter wake-up times.
1k
09997-034
SNR (dBFS)
70
IAVDD
ENCODE FREQUENCY (MSPS)
0.05ps
0.2ps
0.5ps
1ps
1.5ps
MEASURED
75
0.15
0.20
0
40
]
In the equation, the rms aperture jitter represents the root-meansquare of all jitter sources, which include the clock input, the
analog input signal, and the ADC aperture jitter specification.
IF undersampling applications are particularly sensitive to jitter,
as shown in Figure 34.
80
TOTAL POWER
0.10
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input
frequency (fIN) due to jitter (tJ) can be calculated by
2
0.25
SUPPLY CURRENT (A)
The AD6672 contains a DCS that retimes the nonsampling
(falling) edge, providing an internal clock signal with a nominal
50% duty cycle. This allows the user to provide a wide range of
clock input duty cycles without affecting the performance of the
AD6672.
09997-035
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
In cases where aperture jitter may affect the dynamic range of the
AD6672, treat the clock input as an analog signal. In addition,
use separate power supplies for the clock drivers and the ADC
output driver to avoid modulating the clock signal with digital
noise. Low jitter, crystal controlled oscillators provide the best
clock sources. If the clock is generated from another type of
source (by gating, dividing, or another method), it should be
retimed by the original clock during the last step.
TOTAL POWER (W)
Clock Duty Cycle
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. To put the part into standby
mode, set the internal power-down mode bits (Bits[1:0]) in the
power modes register (Address 0x08) to 10. See the Memory
Map section and the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI, for additional details.
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Rev. 0 | Page 19 of 32
AD6672
DIGITAL OUTPUTS
The AD6672 output drivers can be configured for either ANSI
LVDS or reduced swing LVDS using a 1.8 V DRVDD supply.
are available one propagation delay (tPD) after the rising edge of
the clock signal.
Minimize the length of the output data lines as well as the loads
placed on these lines to reduce transients within the AD6672.
These transients may degrade converter dynamic performance.
As detailed in the AN-877 Application Note, Interfacing to High
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI
control.
The lowest typical conversion rate of the AD6672 is 40 MSPS. At
clock rates below 40 MSPS, dynamic performance may degrade.
Digital Output Enable Function (OEB)
Data Clock Output (DCO)
The AD6672 has a flexible three-state ability for the digital
output pins. The three-state mode is enabled using the SPI
interface. The data outputs can be three-stated by using the
output enable bar bit (Bit 4) in Register 0x14. This OEB
function is not intended for rapid access to the data bus.
The AD6672 also provides the data clock output (DCO)
intended for capturing the data in an external register. Figure 2
shows a timing diagram of the AD6672 output modes.
ADC OVERRANGE (OR)
Timing
The AD6672 provides latched data with a pipeline delay of
10 input sample clock cycles when NSR is disabled and provides
13 input sample clock cycles when NSR is enabled. Data outputs
The ADC overrange indicator is asserted when an overrange is
detected on the input of the ADC. The overrange condition is
determined at the output of the ADC pipeline and, therefore, is
subject to a latency of 10 ADC clock cycles. An overrange at the
input is indicated by this bit 10 clock cycles after it occurs.
Table 10. Output Data Format
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−,
Input Span = 1.75 V p-p (V)
<−0.875
−0.875
0
+0.875
>+0.875
Offset Binary Output Mode
000 0000 0000
000 0000 0000
100 0000 0000
111 1111 1111
111 1111 1111
Twos Complement Mode (Default)
100 0000 0000
100 0000 0000
000 0000 0000
011 1111 1111
011 1111 1111
www.BDTIC.com/ADI/
Rev. 0 | Page 20 of 32
OR
1
0
0
0
1
AD6672
NOISE SHAPING REQUANTIZER
Two bandwidth (BW) modes are provided; the mode can be
selected from the SPI port. In each mode, the center frequency
of the band can be tuned such that IFs can be placed anywhere
in the Nyquist band.
0
250MSPS
180.1MHz @ –1.6BFS
SNR = 73.4dB (75.0dBFS)
SFDR = 93dBc (IN BAND)
–20
–40
AMPLITUDE (dBFS)
The AD6672 features a noise shaping requantizer (NSR) to
allow more than an 11-bit SNR to be maintained in a subset of
the Nyquist band. The harmonic performance of the receiver
is unaffected by the NSR feature. When enabled, the NSR
contributes an additional 0.6 dB of loss to the input signal, such
that a 0 dBFS input is reduced to −0.6 dBFS at the output pins.
–60
–80
–100
–120
50
75
FREQUENCY (MHz)
100
125
0
250MSPS
180.1MHz @ –1.6BFS
SNR = 73.3dB (74.9dBFS)
SFDR = 92dBc (IN BAND)
–20
–40
–60
–80
–100
f1 = f0 + 0.22 × fADC
–120
Figure 36 to Figure 38 show the typical spectrum that can be
expected from the AD6672 in the 22% bandwidth mode for
three tuning words.
–140
0
25
50
75
FREQUENCY (MHz)
100
125
Figure 38. 22% Bandwidth Mode, Tuning Word = 41
0
250MSPS
180.1MHz @ –1.6BFS
SNR = 73.4dB (75.0dBFS)
SFDR = 92dBc (IN BAND)
–20
33% BW NSR MODE (>82 MHZ BW AT 250 MSPS)
The 33% bandwidth NSR mode offers excellent noise performance
over 33% of the ADC sample rate (66% of the Nyquist band).
The fundamental can be tuned using a low-pass, band-pass, or
high-pass filter by setting the NSR tuning word bits (Bits[5:0])
in Register 0x3E.
–40
–60
–80
Figure 39 to Figure 41 show the typical spectrum that can be
expected from the AD6672 with the 33% bandwidth NSR mode
enabled for three filter settings.
–100
–120
0
25
50
75
FREQUENCY (MHz)
100
125
09997-036
AMPLITUDE (dBFS)
25
Figure 37. 22% Bandwidth Mode, Tuning Word = 28
fCENTER = f0 + 0.11 × fADC
–140
0
09997-038
f0 = fADC × 0.005 × TW
–140
AMPLITUDE (dBFS)
The first bandwidth mode offers excellent noise performance
over 22% of the ADC sample rate (44% of the Nyquist band)
and can be centered by setting the NSR mode bits (Bits[3:1]) in
the NSR control register (Address 0x3C) to 000. In this mode,
the useful frequency range can be set using the 6-bit tuning
word (Bits[5:0]) in the NSR tuning register (Address 0x3E).
There are 57 possible tuning words (TW); each step is 0.5% of
the ADC sample rate. The following equations describe the left
band edge (f0), the channel center (fCENTER), and the right band
edge (f1), respectively:
09997-037
22% BW NSR MODE (55 MHz BW AT 250 MSPS)
Figure 36. 22% Bandwidth Mode, Tuning Word = 13
www.BDTIC.com/ADI/
Rev. 0 | Page 21 of 32
AD6672
0
0
250MSPS
180.1MHz @ –1.6BFS
SNR = 71.1dB (72.7dBFS)
SFDR = 92dBc (IN BAND)
–20
–20
–40
AMPLITUDE (dBFS)
–60
–80
–100
–80
–100
–120
0
25
50
75
FREQUENCY (MHz)
100
125
09997-039
–120
–60
Figure 39. 33% Bandwidth Mode, Tuning Word = 5
–140
0
25
50
75
FREQUENCY (MHz)
Figure 41. 33% Bandwidth Mode, Tuning Word = 27
0
250MSPS
180.1MHz @ –1.6BFS
SNR = 71.2dB (72.8dBFS)
SFDR = 92dBc (IN BAND)
–20
–60
–80
–100
–120
0
25
50
75
FREQUENCY (MHz)
100
125
09997-040
AMPLITUDE (dBFS)
–40
–140
100
Figure 40. 33% Bandwidth Mode, Tuning Word = 17
www.BDTIC.com/ADI/
Rev. 0 | Page 22 of 32
125
09997-041
AMPLITUDE (dBFS)
–40
–140
250MSPS
180.1MHz @ –1.6BFS
SNR = 70.9dB (72.5dBFS)
SFDR = 92dBc (IN BAND)
AD6672
SERIAL PORT INTERFACE (SPI)
The AD6672 serial port interface (SPI) allows the user to
configure the converter for specific functions or operations
through a structured register space provided inside the ADC.
The SPI offers added flexibility and customization, depending
on the application. Addresses are accessed via the serial port
and can be written to or read from via the port. Memory is
organized into bytes that can be further divided into fields.
These fields are documented in the Memory Map section. For
detailed operational information, see the AN-877 Application
Note, Interfacing to High Speed ADCs via SPI.
CONFIGURATION USING THE SPI
Three pins define the SPI of this ADC: the SCLK pin, the SDIO
pin, and the CSB pin (see Table 11). The SCLK (serial clock) pin
is used to synchronize the read and write data presented from
and to the ADC. The SDIO (serial data input/output) pin is a
dual-purpose pin that allows data to be sent and read from the
internal ADC memory map registers. The CSB (chip select bar)
pin is an active low control that enables or disables the read and
write cycles.
Table 11. Serial Port Interface Pins
Pin
SCLK
SDIO
CSB
Function
Serial clock. The serial shift clock input, which is used to
synchronize serial interface reads and writes.
Serial data input/output. A dual-purpose pin that
typically serves as an input or an output, depending on
the instruction being sent and the relative position in the
timing frame.
Chip select bar. An active low control that gates the read
and write cycles.
The falling edge of CSB, in conjunction with the rising edge of
SCLK, determines the start of the framing. An example of the
serial timing and its definitions can be found in Figure 42 and
Table 5.
Other modes involving the CSB are available. The CSB can be
held low indefinitely, which permanently enables the device;
this is called streaming. The CSB can stall high between bytes
to allow for additional external timing. When CSB is tied high,
SPI functions are placed in a high impedance mode. This mode
turns on any SPI pin secondary functions.
All data is composed of 8-bit words. The first bit of each
individual byte of serial data indicates whether a read or write
command is issued. This allows the serial data input/output
(SDIO) pin to change direction from an input to an output.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. If the instruction is a
readback operation, performing a readback causes the serial
data input/output (SDIO) pin to change direction from an input
to an output at the appropriate point in the serial frame.
Data can be sent in MSB first mode or in LSB first mode. MSB
first mode is the default on power-up and can be changed via
the SPI port configuration register. For more information about
this and other features, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
HARDWARE INTERFACE
The pins described in Table 11 comprise the physical interface
between the user programming device and the serial port of the
AD6672. The SCLK pin and the CSB pin function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used
for other devices, it may be necessary to provide buffers
between this bus and the AD6672 to prevent these signals from
transitioning at the converter inputs during critical sampling
periods.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and its length is determined
by the W0 and W1 bits.
www.BDTIC.com/ADI/
Rev. 0 | Page 23 of 32
AD6672
SPI ACCESSIBLE FEATURES
Table 12 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the AN-877 Application Note, Interfacing to High Speed ADCs
via SPI. The AD6672 part-specific features are described in the
Memory Map Register Description section.
Table 12. Features Accessible Using the SPI
Feature Name
Mode
Clock
Offset
Test I/O
Output Mode
Output Phase
Output Delay
VREF
Digital Processing
Description
Allows the user to set either power-down mode or standby mode
Allows the user to access the DCS via the SPI
Allows the user to digitally adjust the converter offset
Allows the user to set test modes to have known data on output bits
Allows the user to set up outputs
Allows the user to set the output clock polarity
Allows the user to vary the DCO delay
Allows the user to set the reference voltage
Allows the user to enable the synchronization features
tHIGH
tDS
tS
tDH
tCLK
tH
tLOW
CSB
SCLK DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
DON’T CARE
09997-042
SDIO DON’T CARE
DON’T CARE
Figure 42. Serial Port Interface Timing Diagram
www.BDTIC.com/ADI/
Rev. 0 | Page 24 of 32
AD6672
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Each row in the memory map register table has eight bit locations.
The memory map is roughly divided into four sections: the chip
configuration registers (Address 0x00 to Address 0x02); the transfer
register (Address 0xFF); the ADC functions registers, including
setup, control, and test (Address 0x08 to Address 0x25); and the
digital feature control registers (Address 0x3C and Address 0x3E).
The memory map register table (Table 13) documents the
default hexadecimal value for each hexadecimal address shown.
The Bit 7 (MSB) column is the start of the default hexadecimal
value given. For example, Address 0x14, the output mode
register, has a hexadecimal default value of 0x01. This means
that Bit 0 = 1 and the remaining bits are 0s. This setting is the
default output format value, which is twos complement. For
more information on this function and others, see the AN-877
Application Note, Interfacing to High Speed ADCs via SPI. This
document details the functions controlled by Register 0x00 to
Register 0x25. The remaining registers, Register 0x3C and
Register 0x3E, are documented in the Memory Map Register
Description section.
Open Locations
All address and bit locations that are not included in Table 13
are not currently supported for this device. Write 0s to unused
bits of a valid address location. Writing to these locations is
required only when part of an address location is open (for
example, Address 0x18). If the entire address location is open
(for example, Address 0x13), this address location should not be
written.
Default Values
After the AD6672 is reset, critical registers are loaded with
default values. The default values for the registers are given in
the memory map register table (Table 13).
Logic Levels
An explanation of logic level terminology follows:
•
•
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
Transfer Register Map
Address 0x08 to Address 0x20, as well as Address 0x3C and
Address 0x3E, are shadowed. Writes to these addresses do not
affect part operation until a transfer command is issued by
writing 0x01 to Address 0xFF, setting the transfer bit. This allows
these registers to be updated internally and simultaneously when
the transfer bit is set. The internal update takes place when the
transfer bit is set, and then the bit autoclears.
www.BDTIC.com/ADI/
Rev. 0 | Page 25 of 32
AD6672
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 13 are not currently supported for this device.
Table 13. Memory Map Registers
Addr
Register
Bit 7
(Hex)
Name
(MSB)
Chip Configuration Registers
0x00
0
SPI port
configuration
0x01
Chip ID
0x02
Chip grade
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
LSB first
Soft reset
1
1
Soft reset
LSB first
0
8-bit chip ID[7:0]
(AD6672 = 0xA4)
(default)
Speed grade ID
Open
00 = 250 MSPS
Open
Open
Transfer Register
0xFF
Transfer
Open
Open
Open
Open
ADC Functions Registers
0x08
Power modes
Open
Open
Open
0x09
Global clock
Open
Open
Open
0x0B
Clock divide
Open
Open
0x0D
Test mode
User test
mode
control
0 = continuous/
repeat
pattern
1=
single
pattern,
then 0s
Open
Reset PN
long gen
Reset PN
short gen
0x0E
BIST enable
Open
Open
Open
Open
Open
Open
Open
Open
Open
Transfer
Open
Open
Open
Open
Open
Internal power-down
mode
00 = normal operation
01 = full power-down
10 = standby
11 = reserved
Open
Open
Duty
cycle
stabilizer
(default)
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
Output test mode
0000 = off (default)
0001 = midscale short
0010 = positive FS
0011 = negative FS
0100 = alternating checkerboard
0101 = PN long sequence
0110 = PN short sequence
0111 = one/zero word toggle
1000 = user test mode
1001 to 1110 = unused
1111 = ramp output
Open
Open
Reset BIST
sequence
0x18
Nibbles are
mirrored so
that LSB
first mode
or MSB first
mode is set
correctly,
regardless
of shift
mode.
Read only.
Speed
grade ID
used to differentiate
devices;
read only.
0x00
Synchronously
transfers
data from
the master
shift
register to
the slave.
0x00
Determines
various
generic
modes
of chip
operation.
0x01
0x00
0x00
BIST
enable
www.BDTIC.com/ADI/
Rev. 0 | Page 26 of 32
Default
Notes/
Comments
0xA4
Open
Input clock divider phase adjust
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
Default
Value
(Hex)
0x00
Clock
divide
values
other than
000 automatically
cause the
duty cycle
stabilizer
to become
active.
When this
register is
set, the
test data is
placed on
the output
pins in
place of
normal
data.
AD6672
Addr
(Hex)
0x10
Register
Name
Offset adjust
Bit 7
(MSB)
Open
Bit 6
Open
Bit 5
0x14
Output mode
Open
Open
Open
0x15
Output adjust
Open
Open
Open
0x16
Clock phase
control
Open
Open
0x17
DCO output
delay
Invert
DCO
clock
Enable
DCO
clock
delay
Open
Open
0x18
Input span
select
Open
Open
Open
0x19
User Test
Pattern 1 LSB
0x1A
User Test
Pattern 1 MSB
0x1B
User Test
Pattern 2 LSB
0x1C
User Test
Pattern 2 MSB
0x1D
User Test
Pattern 3 LSB
0x1E
User Test
Pattern 3 MSB
0x1F
User Test
Pattern 4 LSB
0x20
User Test
Pattern 4 MSB
0x24
BIST signature
LSB
0x25
BIST signature
MSB
Digital Feature Control Registers
0x3C
NSR control
Open
Open
0x3E
Open
NSR tuning
word
Open
Open
Bit 0
(LSB)
Bit 4
Bit 3
Bit 2
Bit 1
Offset adjust in LSBs from +31 to −32
(twos complement format)
Open
Output format
Output
Output
enable bar
invert
00 = offset binary
0 = on
0 = normal
01 = twos complement
1 = off
(default)
(default)
1=
10 = gray code
inverted
11 = reserved
Open
LVDS output drive current adjust
0000 = 3.72 mA output drive current
0001 = 3.5 mA output drive current (default)
0010 = 3.30 mA output drive current
0011 = 2.96 mA output drive current
0100 = 2.82 mA output drive current
0101 = 2.57 mA output drive current
0110 = 2.27 mA output drive current
0111 = 2.0 mA output drive current (reduced range)
1000 to 1111 = reserved
Open
Open
Open
Open
Open
Default
Value
(Hex)
0x00
Default
Notes/
Comments
0x01
Configures
the
outputs
and the
format of
the data.
0x01
0x00
DCO clock delay
[delay = (3100 ps × register value/31 +100)]
00000 = 100 ps
00001 = 200 ps
00010 = 300 ps
…
11110 = 3100 ps
11111 = 3200 ps
Full-scale input voltage selection
01111 = 2.087 V p-p
…
00001 = 1.772 V p-p
00000 = 1.75 V p-p (default)
11111 = 1.727 V p-p
…
10000 = 1.383 V p-p
User Test Pattern 1[7:0]
0x00
User Test Pattern 1[15:8]
0x00
User Test Pattern 2[7:0]
0x00
User Test Pattern 2[15:8]
0x00
User Test Pattern 3[7:0]
0x00
User Test Pattern 3[15:8]
0x00
User Test Pattern 4[7:0]
0x00
User Test Pattern 4[15:8]
0x00
BIST signature[7:0]
0x00
Read only.
BIST signature[15:8]
0x00
Read only.
0x00
NSR
controls.
0x1C
NSR frequency
tuning
word.
Open
NSR mode
000 = 22% bandwidth mode
001 = 33% bandwidth mode
NSR
enable
0 = off
1 = on
NSR tuning word
(see the Noise Shaping Requantizer section;
equations for the tuning word are dependent on the NSR mode)
www.BDTIC.com/ADI/
Rev. 0 | Page 27 of 32
0x00
Full-scale
input
adjustment
in 0.022 V
steps.
0x00
AD6672
MEMORY MAP REGISTER DESCRIPTION
Bit 0—NSR Enable
For more information on functions controlled in Register 0x00
to Register 0x25, see the AN-877 Application Note, Interfacing
to High Speed ADCs via SPI.
The NSR is enabled when Bit 0 is high and disabled when Bit 0
is low.
NSR Control (Register 0x3C)
Bits[7:4]—Reserved
NSR Tuning Word (Register 0x3E)
Bits[7:6]—Reserved
Bits[5:0]—NSR Tuning Word
Bits[3:1]—NSR Mode
Bits[3:1] determine the bandwidth mode of the NSR. When
Bits[3:1] are set to 000, the NSR is configured for 22%
bandwidth mode, which provides enhanced SNR performance
over 22% of the sample rate. When Bits[3:1] are set to 001, the
NSR is configured for 33% bandwidth mode, which provides
enhanced SNR performance over 33% of the sample rate.
The NSR tuning word sets the band edges of the NSR band. In
22% bandwidth mode, there are 57 possible tuning words; in
33% bandwidth mode, there are 34 possible tuning words. In
either mode, each step represents 0.5% of the ADC sample rate.
For the equations that are used to calculate the tuning word
based on the bandwidth mode of operation, see the Noise
Shaping Requantizer section.
www.BDTIC.com/ADI/
Rev. 0 | Page 28 of 32
AD6672
APPLICATIONS INFORMATION
DESIGN GUIDELINES
VCM
Before starting system level design and layout of the AD6672,
it is recommended that the designer become familiar with these
guidelines, which discuss the special circuit connections and
layout requirements for certain pins.
Decouple the VCM pin to ground with a 0.1 μF capacitor, as
shown in Figure 26.
Power and Ground Recommendations
When connecting power to the AD6672, it is recommended that
two separate 1.8 V supplies be used: use one supply for analog
(AVDD) and a separate supply for the digital outputs (DRVDD).
The designer can employ several different decoupling capacitors
to cover both high and low frequencies. Locate these capacitors
close to the point of entry at the PC board level and close to the
pins of the part with minimal trace length.
SPI Port
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK, CSB, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices,
it may be necessary to provide buffers between this bus and the
AD6672 to keep these signals from transitioning at the
converter input pins during critical sampling periods.
A single PCB ground plane should be sufficient when using the
AD6672. With proper decoupling and smart partitioning of the
PCB analog, digital, and clock sections, optimum performance
can be easily achieved.
Exposed Paddle Thermal Heat Slug Recommendations
It is mandatory that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance. A continuous, exposed
(no solder mask) copper plane on the PCB should mate to the
AD6672 exposed paddle, Pin 0.
The copper plane should have several vias to achieve the lowest
possible resistive thermal path for heat dissipation to flow
through the bottom of the PCB. These vias should be filled or
plugged with nonconductive epoxy.
To maximize the coverage and adhesion between the ADC
and the PCB, overlay a silkscreen to partition the continuous
plane on the PCB into several uniform sections. This provides
several tie points between the ADC and the PCB during the
reflow process. Using one continuous plane with no partitions
guarantees only one tie point between the ADC and the PCB.
See the evaluation board for a PCB layout example. For detailed
information about the packaging and PCB layout of chip scale
packages, refer to the AN-772 Application Note, A Design and
Manufacturing Guide for the Lead Frame Chip Scale Package
(LFCSP).
www.BDTIC.com/ADI/
Rev. 0 | Page 29 of 32
AD6672
OUTLINE DIMENSIONS
0.30
0.25
0.18
32
25
1
24
0.50
BSC
*3.75
EXPOSED
PAD
3.60 SQ
3.55
17
TOP VIEW
0.80
0.75
0.70
0.50
0.40
0.30
8
16
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
PIN 1
INDICATOR
9
BOTTOM VIEW
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
*COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5
WITH EXCEPTION TO EXPOSED PAD DIMENSION.
08-16-2010-B
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
Figure 43. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5 mm Body, Very Very Thin Quad
(CP-32-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD6672BCPZ-250
AD6672BCPZRL7-250
AD6672-250EBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Evaluation Board with AD6672 and Software
Package Option
CP-32-12
CP-32-12
Z = RoHS Compliant Part.
www.BDTIC.com/ADI/
Rev. 0 | Page 30 of 32
AD6672
NOTES
www.BDTIC.com/ADI/
Rev. 0 | Page 31 of 32
AD6672
NOTES
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09997-0-7/11(0)
www.BDTIC.com/ADI/
Rev. 0 | Page 32 of 32
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