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AD5253 数据手册DataSheet下载
Quad 64-/256-Position I2C Nonvolatile
Memory Digital Potentiometers
AD5253/AD5254
FEATURES
APPLICATIONS
Mechanical potentiometer replacement
Low resolution DAC replacement
RGB LED backlight control
White LED brightness adjustment
RF base station power amp bias control
Programmable gain and offset control
Programmable attenuators
Programmable voltage-to-current conversion
Programmable power supply
Programmable filters
Sensor calibrations
GENERAL DESCRIPTION
The AD5253/AD5254 are quad-channel, I2C®, nonvolatile
mem-ory, digitally controlled potentiometers with 64/256
positions, respectively. These devices perform the same
electronic adjust-ment functions as mechanical potentiometers,
trimmers, and variable resistors.
The parts’ versatile programmability allows multiple modes of
operation, including read/write access in the RDAC and EEMEM
registers, increment/decrement of resistance, resistance changes
in ±6 dB scales, wiper setting readback, and extra EEMEM for
storing user-defined information, such as memory data for other
components, look-up table, or system identification information.
FUNCTIONAL BLOCK DIAGRAM
RDAC EEMEM
VDD
VSS
DGND
EEMEM
POWER-ON
REFRESH
RAB TOL
RDAC0
RDAC0
REGISTER
A0
W0
B0
WP
SCL
SDA
AD0
AD1
DATA
I2C
SERIAL
INTERFACE
CONTROL
COMMAND
DECODE LOGIC
ADDRESS
DECODE LOGIC
RDAC1
RDAC1
REGISTER
A1
W1
B1
RDAC2
RDAC2
REGISTER
A2
W2
B2
CONTROL LOGIC
RDAC3
RDAC3
REGISTER
AD5253/AD5254
A3
W3
B3
03824-0-001
AD5253: quad 64-position resolution
AD5254: quad 256-position resolution
1 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Nonvolatile memory 1 stores wiper settings w/write protection
Power-on refreshed to EEMEM settings in 300 μs typ
EEMEM rewrite time = 540 μs typ
Resistance tolerance stored in nonvolatile memory
12 extra bytes in EEMEM for user-defined information
I2C-compatible serial interface
Direct read/write access of RDAC 2 and EEMEM registers
Predefined linear increment/decrement commands
Predefined ±6 dB step change commands
Synchronous or asynchronous quad-channel update
Wiper setting readback
4 MHz bandwidth—1 kΩ version
Single supply 2.7 V to 5.5 V
Dual supply ±2.25 V to ±2.75 V
2 slave address-decoding bits allow operation of 4 devices
100-year typical data retention, TA = 55°C
Operating temperature: –40°C to +85°C
Figure 1.
The AD5253/AD5254 allow the host I2C controllers to write
any of the 64-/256-step wiper settings in the RDAC registers
and store them in the EEMEM. Once the settings are stored,
they are restored automatically to the RDAC registers at system
power-on; the settings can also be restored dynamically.
The AD5253/AD5254 provide additional increment,
decrement, +6 dB step change, and –6 dB step change in
synchronous or asynchronous channel update mode. The
increment and decrement functions allow stepwise linear
adjustments, with a ± 6 dB step change equivalent to doubling
or halving the RDAC wiper setting. These functions are useful
for steep-slope, nonlinear adjustments, such as white LED
brightness and audio volume control.
The AD5253/AD5254 have a patented resistance-tolerance
storing function that allows the user to access the EEMEM and
obtain the absolute end-to-end resistance values of the RDACs
for precision applications.
The AD5253/AD5254 are available in TSSOP-20 packages in
1 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ options. All parts are
guaranteed to operate over the –40°C to +85°C extended
industrial temperature range.
1
The terms nonvolatile memory and EEMEM are used interchangeably.
The terms digital potentiometer and RDAC are used interchangeably.
2
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2003–2009 Analog Devices, Inc. All rights reserved.
www.BDTIC.com/ADI
AD5253/AD5254
TABLE OF CONTENTS
Features .............................................................................................. 1 I2C-Compatible 2-Wire Serial Bus ........................................... 20 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 21 General Description ......................................................................... 1 Linear Increment/Decrement Commands ............................. 21 Functional Block Diagram .............................................................. 1 ±6 dB Adjustments (Doubling/Halving Wiper Setting) ....... 21 Revision History ............................................................................... 2 Digital Input/Output Configuration........................................ 22 Electrical Characteristics ................................................................. 3 Multiple Devices on One Bus ................................................... 22 1 kΩ Version.................................................................................. 3 Terminal Voltage Operation Range ......................................... 23 10 kΩ, 50 kΩ, 100 kΩ Versions .................................................. 5 Power-Up and Power-Down Sequences .................................. 23 Interface Timing Characteristics ................................................ 7 Layout and Power Supply Biasing ............................................ 23 Absolute Maximum Ratings............................................................ 8 Digital Potentiometer Operation ............................................. 24 ESD Caution .................................................................................. 8 Programmable Rheostat Operation ......................................... 24 Pin Configuration and Function Descriptions ............................. 9 Programmable Potentiometer Operation ............................... 25 Typical Performance Characteristics ........................................... 10 Applications Information .............................................................. 26 I2C Interface ..................................................................................... 14 RGB LED Backlight Controller for LCD Panels .................... 26 I2C Interface General Description ............................................ 14 Outline Dimensions ....................................................................... 28 I2C Interface Detail Description ............................................... 15 Ordering Guide .......................................................................... 29 REVISION HISTORY
10/09—Rev. A to Rev. B
Change to Figure 27 ....................................................................... 15
9/05—Rev. 0 to Rev. A
Change to Figure 6 ......................................................................... 10
Change to EEMEM Write Protection Section ............................ 18
Changes to Figure 37 ...................................................................... 22
Deleted Table 13 and Table 14 ...................................................... 24
Change to Figure 43 ....................................................................... 25
Changes to Ordering Guide .......................................................... 29
5/03—Revision 0: Initial Version
Rev. B | Page 2 of 32
www.BDTIC.com/ADI
AD5253/AD5254
ELECTRICAL CHARACTERISTICS
1 kΩ VERSION
VDD = +3 V ± 10% or +5 V ± 10%, VSS = 0 V or VDD/VSS = ±2.5 V ± 10%, VA = VDD, VB = 0 V, –40°C < TA < +85°C, unless otherwise noted.
Table 1.
Parameter
DC CHARACTERISTICS—
RHEOSTAT MODE
Resolution
Symbol
Conditions
N
AD5253
AD5254
RWB, RWA = NC, VDD = 5.5 V, AD5253
RWB, RWA = NC, VDD = 5.5 V, AD5254
RWB, RWA = NC, VDD = 2.7 V, AD5253
RWB, RWA = NC, VDD = 2.7 V, AD5254
RWB, RWA = NC, VDD = 5.5 V, AD5253
RWB, RWA = NC, VDD = 5.5 V, AD5254
RWB, RWA = NC, VDD = 2.7 V, AD5253
RWB, RWA = NC, VDD = 2.7 V, AD5254
TA = 25°C
Resistor Differential Nonlinearity 2
R-DNL
Resistor Nonlinearity2
R-INL
Nominal Resistor Tolerance
Resistance Temperature Coefficient
Wiper Resistance
ΔRAB/RAB
(ΔRAB/RAB) × 106/ΔT
RW
Channel-Resistance Matching
DC CHARACTERISTICS—
POTENTIOMETER DIVIDER MODE
Differential Nonlinearity 3
–0.5
–1.00
–0.75
–1.5
–0.5
–2.0
–1.0
–2
–30
DNL
INL
Voltage Divider Tempco
Full-Scale Error
(ΔVW/VW) × 106/ΔT
VWFSE
Zero-Scale Error
VWZSE
VA, VB, VW
CA, CB
Capacitance5 W
CW
Common-Mode Leakage Current
ICM
Typ 1
±0.2
±0.25
±0.30
±0.3
±0.2
±0.5
+2.5
+9
650
75
200
0.15
IW = 1 V/R, VDD = 5 V
IW = 1 V/R, VDD = 3 V
ΔRAB1/ΔRAB2
Integral Nonlinearity3
RESISTOR TERMINALS
Voltage Range 4
Capacitance 5 A, B
Min
AD5253
AD5254
AD5253
AD5254
Code = half scale
Code = full scale, VDD = 5.5 V, AD5253
Code = full scale, VDD = 5.5 V, AD5254
Code = full scale, VDD = 2.7 V, AD5253
Code = full scale, VDD = 2.7 V, AD5254
Code = zero scale, VDD = 5.5 V, AD5253
Code = zero scale, VDD = 5.5 V, AD5254
Code = zero scale, VDD = 2.7 V, AD5253
Code = zero scale, VDD = 2.7 V, AD5254
–0.5
–1.00
–0.5
–2.0
–5
–16
–6
–23
0
0
0
0
±0.1
±0.25
±0.2
±0.5
25
–3
–11
–4
–16
3
11
4
15
VSS
f = 1 kHz, measured to GND,
code = half scale
f = 1 kHz, measured to GND,
code = half scale
VA = VB = VDD/2
Max
Unit
6
8
+0.5
+1.00
+0.75
+1.5
+0.5
+2.0
+4.0
+14
+30
Bits
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
%
ppm/°C
Ω
Ω
%
130
300
+0.5
+1.00
+0.5
+2.0
0
0
0
0
5
16
6
20
VDD
LSB
LSB
LSB
LSB
ppm/°C
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
85
V
pF
95
pF
0.01
1.00
Rev. B | Page 3 of 32
www.BDTIC.com/ADI
μA
AD5253/AD5254
Parameter
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Output Logic High (SDA)
Output Logic Low (SDA)
WP Leakage Current
A0 Leakage Current
Input Leakage Current
(Other than WP and A0)
Input Capacitance5
POWER SUPPLIES
Single-Supply Power Range
Dual-Supply Power Range
Positive Supply Current
Negative Supply Current
EEMEM Data Storing Mode Current
EEMEM Data Restoring Mode
Current 6
Power Dissipation 7
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS5, 8
Bandwidth –3 dB
Total Harmonic Distortion
VW Settling Time
Resistor Noise Voltage
Symbol
Conditions
Min
VIH
VDD = 5 V, VSS = 0 V
VDD/VSS = +2.7 V/0 V or VDD/VSS = ±2.5 V
VDD = 5 V, VSS = 0 V
VDD/VSS = +2.7 V/0 V or VDD/VSS = ±2.5 V
RPULL-UP = 2.2 kΩ to VDD = 5 V, VSS = 0 V
RPULL-UP = 2.2 kΩ to VDD = 5 V, VSS = 0 V
WP = VDD
A0 = GND
VIN = 0 V or VDD
2.4
2.1
VIL
VOH
VOL
IWP
IA0
II
IDD_STORE
IDD_RESTORE
4.9
0.4
5
3
±1
5
VSS = 0 V
2.7
±2.25
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND, VDD = 2.5 V,
VSS = –2.5 V
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND
5
–5
VIH = VDD = 5 V or VIL = GND
ΔVDD = 5 V ± 10%
ΔVDD = 3 V ± 10%
BW
THD
tS
eN_WB
RAB = 1 kΩ
VA =1 V rms, VB = 0 V, f = 1 kHz
VA = VDD, VB = 0 V
RWB = 500 Ω, f = 1 kHz
(thermal noise only)
VA = VDD, VB = 0 V, measure VW with
adjacent RDAC making full-scale
change
Signal input at A0 and measure the
output at W1, f = 1 kHz
CT
Analog Coupling
CAT
−0.025
–0.04
+0.010
+0.02
Unit
V
V
V
V
V
V
μA
μA
μA
pF
5.5
±2.75
15
–15
35
2.5
PDISS
PSS
Digital Crosstalk
Max
0.8
0.6
CI
VDD
VDD/VSS
IDD
ISS
Typ 1
V
V
μA
μA
mA
mA
0.075
+0.025
+0.04
mW
%/%
%/%
4
0.05
0.2
3
MHz
%
μs
nV/√Hz
–80
dB
–72
dB
1
Typical values represent average readings at 25°C and VDD = 5 V.
Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL is the
relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5254 1 kΩ version at VDD = 2.7 V,
IW = VDD/R for both VDD = 3 V and VDD = 5 V.
3
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
4
Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.
5
Guaranteed by design and not subject to production test.
6
Command 0 NOP should be activated after Command 1 to minimize IDD_RESTORE current consumption.
7
PDISS is calculated from IDD × VDD = 5 V.
8
All dynamic characteristics use VDD = 5 V.
2
Rev. B | Page 4 of 32
www.BDTIC.com/ADI
AD5253/AD5254
10 kΩ, 50 kΩ, 100 kΩ VERSIONS
VDD = +3 V ± 10% or +5 V ± 10%, VSS = 0 V or VDD/VSS = ±2.5 V ± 10%, VA = VDD, VB = 0 V, –40°C < TA < +85°C, unless otherwise noted.
Table 2.
Parameter
DC CHARACTERISTICS—
RHEOSTAT MODE
Resolution
Resistor Differential Nonlinearity 2
Symbol
Conditions
Min
Typ 1
Max
Unit
N
R-DNL
AD5253/AD5254
RWB, RWA = NC, AD5253
RWB, RWA = NC, AD5254
RWB, RWA = NC, AD5253
RWB, RWA = NC, AD5254
TA = 25°C
−0.75
−1.00
−0.75
−2.5
−20
±0.10
±0.25
±0.25
±1.0
6/8
+0.75
+1.00
+0.75
+2.5
+20
Bits
LSB
LSB
LSB
LSB
%
ppm/°C
75
200
0.15
0.05
130
300
Ω
Ω
%
%
Resistor Nonlinearity2
R-INL
Nominal Resistor Tolerance
Resistance Temperature
Coefficient
Wiper Resistance
ΔRAB/RAB
(ΔRAB/RAB) × 106/ΔT
Channel-Resistance Matching
ΔRAB1/ΔRAB2
DC CHARACTERISTICS—
POTENTIOMETER DIVIDER MODE
Differential Nonlinearity 3
RW
DNL
Integral Nonlinearity3
INL
Voltage Divider
Temperature Coefficient
Full-Scale Error
(ΔVW/VW) × 106/ΔT
Zero-Scale Error
VWZSE
RESISTOR TERMINALS
Voltage Range 4
Capacitance 5 A, B
Capacitance5 W
Common-Mode Leakage Current
DIGITAL INPUTS AND OUTPUTS
Input Logic High
VWFSE
VA, VB, VW
CA, CB
CW
ICM
VIH
Input Logic Low
VIL
Output Logic High (SDA)
Output Logic Low (SDA)
WP Leakage Current
A0 Leakage Current
Input Leakage Current
(Other than WP and A0)
Input Capacitance5
VOH
VOL
IWP
IA0
II
650
IW = 1 V/R, VDD = 5 V
IW = 1 V/R, VDD = 3 V
RAB = 10 kΩ, 50 kΩ
RAB = 100 kΩ
AD5253
AD5254
AD5253
AD5254
Code = half scale
−0.5
−1.0
−0.50
−1.5
±0.1
±0.3
±0.15
±0.5
15
+0.5
+1.0
+0.50
+1.5
LSB
LSB
LSB
LSB
ppm/°C
Code = full scale, AD5253
Code = full scale, AD5254
Code = zero scale, AD5253
Code = zero scale, AD5254
−1.0
−3
0
0
−0.3
−1
0.3
1.2
0
0
1.0
3.0
LSB
LSB
LSB
LSB
VDD
85
V
pF
95
pF
VSS
f = 1 kHz, measured to GND,
code = half scale
f = 1 kHz, measured to GND,
code = half scale
VA = VB = VDD/2
0.01
VDD = 5 V, VSS = 0 V
VDD/VSS = +2.7 V/0 V or VDD/VSS = ±2.5 V
VDD = 5 V, VSS = 0 V
VDD/VSS = +2.7 V/0 V or VDD/VSS = ±2.5 V
RPULL-UP = 2.2 kΩ to VDD = 5 V, VSS = 0 V
RPULL-UP = 2.2 kΩ to VDD = 5 V, VSS = 0 V
WP = VDD
A0 = GND
VIN = 0 V or VDD
CI
1
2.4
2.1
0.8
0.6
4.9
0.4
5
3
±1
5
Rev. B | Page 5 of 32
www.BDTIC.com/ADI
μA
V
V
V
V
V
V
μA
μA
μA
pF
AD5253/AD5254
Parameter
POWER SUPPLIES
Single-Supply Power Range
Dual-Supply Power Range
Positive Supply Current
Negative Supply Current
EEMEM Data Storing Mode
Current
EEMEM Data Restoring Mode
Current 6
Power Dissipation 7
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS5, 8
–3 dB Bandwidth
Total Harmonic Distortion
VW Settling Time
Typ 1
Max
Unit
5
−5
V
V
μA
μA
IDD_STORE
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND, VDD = 2.5 V,
VSS = −2.5 V
VIH = VDD or VIL = GND, TA = 0°C to 85°C
5.5
±2.75
15
−15
35
mA
IDD_RESTORE
VIH = VDD or VIL = GND, TA = 0°C to 85°C
2.5
mA
PDISS
PSS
VIH = VDD = 5 V or VIL = GND
ΔVDD = 5 V ± 10%
ΔVDD = 3 V ± 10%
BW
THDW
tS
RAB = 10 kΩ/50 kΩ/100 kΩ
VA = 1 V rms, VB = 0 V, f = 1 kHz
VA = VDD, VB = 0 V,
RAB = 10 kΩ/50 kΩ/100 kΩ
RAB = 10 kΩ/50 kΩ/100 kΩ, code =
midscale, f = 1 kHz (thermal noise only)
VA = VDD, VB = 0 V, measure VW with
adjacent RDAC making full-scale change
Signal input at A0 and measure output
at W1, f = 1 kHz
Symbol
Conditions
Min
VDD
VDD/VSS
IDD
ISS
VSS = 0 V
2.7
±2.25
Resistor Noise Voltage
eN_WB
Digital Crosstalk
CT
Analog Coupling
CAT
−0.005
−0.010
+0.002
+0.002
0.075
+0.005
+0.010
mW
%/%
%/%
400/80/40
0.05
1.5/7/14
kHz
%
μs
9/20/29
nV/√Hz
−80
dB
−72
dB
1
Typical values represent average readings at 25°C and VDD = 5 V.
Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL is the
relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5254 1 kΩ version at VDD = 2.7 V,
IW = VDD/R for both VDD = 3 V and VDD = 5 V.
3
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider, similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
4
Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.
5
Guaranteed by design and not subject to production test.
6
Command 0 NOP should be activated after Command 1 to minimize IDD_RESTORE current consumption.
7
PDISS is calculated from IDD × VDD = 5 V.
8
All dynamic characteristics use VDD = 5 V.
2
Rev. B | Page 6 of 32
www.BDTIC.com/ADI
AD5253/AD5254
INTERFACE TIMING CHARACTERISTICS
All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching
characteristics are measured using both VDD = 3 V and 5 V.
Table 3.
Parameter 1
INTERFACE TIMING
SCL Clock Frequency
tBUF Bus-Free Time Between Stop and Start
tHD;STA Hold Time (Repeated Start)
Symbol
fSCL
t1
t2
tLOW Low Period of SCL Clock
tHIGH High Period of SCL Clock
tSU;STA Set-up Time for Start Condition
tHD;DAT Data Hold Time
tSU;DAT Data Set-up Time
tF Fall Time of Both SDA and SCL Signals
tR Rise Time of Both SDA and SCL Signals
tSU;STO Set-up Time for Stop Condition
EEMEM Data Storing Time
EEMEM Data Restoring Time at Power-On 3
t3
t4
t5
t6
t7
t8
t9
t10
tEEMEM_STORE
tEEMEM_RESTORE1
EEMEM Data Restoring Time upon Restore
Command or Reset Operation3
EEMEM Data Rewritable Time 4
FLASH/EE MEMORY RELIABILITY
Endurance 5
Data Retention 6, 7
tEEMEM_RESTORE2
Conditions
Min
After this period, the first clock pulse is
generated.
Typ 2
Max
Unit
400
kHz
μs
μs
1.3
0.6
1.3
0.6
0.6
0
100
26
300
μs
μs
μs
μs
ns
ns
ns
μs
ms
μs
300
μs
540
μs
100
K cycles
Years
0.9
300
300
0.6
VDD rise time dependent. Measure without
decoupling capacitors at VDD and VSS.
VDD = 5 V.
tEEMEM_REWRITE
100
1
See Figure 23 for location of measured values.
Typical values represent average readings at 25°C and VDD = 5 V.
3
During power-up, all outputs are preset to midscale before restoring the EEMEM contents. RDAC0 has the shortest EEMEM restore time, whereas RDAC3 has the longest.
4
Delay time after power-on or reset before new EEMEM data to be written.
5
Endurance is qualified to 100,000 cycles per JEDEC Std. 22 Method A117 and measured at –40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.
6
Retention lifetime equivalent at junction temperature TJ = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates
with junction temperature.
7
When the part is not in operation, the SDA and SCL pins should be pulled high. When these pins are pulled low, the I2C interface at these pins conducts a current of
about 0.8 mA at VDD = 5.5 V and 0.2 mA at VDD = 2.7 V.
2
Rev. B | Page 7 of 32
www.BDTIC.com/ADI
AD5253/AD5254
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted
Table 4.
Parameter
VDD to GND
VSS to GND
VDD to VSS
VA, VB, VW to GND
Maximum Current
IWB, IWA Pulsed
IWB Continuous (RWB ≤ 1 kΩ, A Open) 1
IWA Continuous (RWA ≤ 1 kΩ, B Open)1
IAB Continuous
(RAB = 1 kΩ/10 kΩ/50 kΩ/100 kΩ)1
Digital Inputs and Output Voltage to GND
Operating Temperature Range
Maximum Junction Temperature (TJMAX)
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
TSSOP-20 Thermal Resistance 2 θJA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
−0.3 V, +7 V
+0.3 V, −7 V
7V
VSS, VDD
±20 mA
±5 mA
±5 mA
±5 mA/±500 μA/
±100 μA/±50 μA
0 V, 7 V
−40°C to +85°C
150°C
−65°C to +150°C
300°C
215°C
220°C
143°C/W
ESD CAUTION
1
Maximum terminal current is bound by the maximum applied voltage across
any two of the A, B, and W terminals at a given resistance, the maximum
current handling of the switches, and the maximum power dissipation of the
package. VDD = 5 V.
2
Package power dissipation = (TJMAX − TA)/θJA.
Rev. B | Page 8 of 32
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AD5253/AD5254
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
W0 1
B0 2
AD5253/
AD5254
A0 3
20
VDD
19
W3
18
B3
17 A3
TOP VIEW
WP 5 (Not to Scale) 16 AD1
W1 6
15
DGND
B1 7
14
SCL
A1 8
13
W2
SDA 9
12
B2
VSS 10
11
A2
03824-0-002
AD0 4
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
Mnemonic
W0
B0
A0
AD0
WP
W1
B1
A1
SDA
10
VSS
11
12
13
14
A2
B2
W2
SCL
15
16
17
18
19
20
DGND
AD1
A3
B3
W3
VDD
Description
Wiper Terminal of RDAC0. VSS ≤ VW0 ≤ VDD.
B Terminal of RDAC0. VSS ≤ VB0 ≤ VDD.
A Terminal of RDAC0. VSS ≤ VA0 ≤ VDD.
I2C Device Address 0. AD0 and AD1 allow four AD5253/AD5254 devices to be addressed.
Write Protect, Active Low. VWP ≤ VDD + 0.3 V.
Wiper Terminal of RDAC1. VSS ≤ VW1 ≤ VDD.
B Terminal of RDAC1. VSS ≤ VB1 ≤ VDD.
A Terminal of RDAC1. VSS ≤ VA1 ≤ VDD.
Serial Data Input/Output Pin. Shifts in one bit at a time upon positive clock edges. MSB loaded first. Open-drain
MOSFET requires pull-up resistor.
Negative Supply. Connect to 0 V for single supply or –2.7 V for dual supply, where VDD – VSS ≤ +5.5 V. If VSS is used
rather than grounded in dual supply, VSS must be able to sink 35 mA for 26 ms when storing data to EEMEM.
A Terminal of RDAC2. VSS ≤ VA2 ≤ VDD.
B Terminal of RDAC2. VSS ≤ VB2 ≤ VDD.
Wiper Terminal of RDAC2. VSS ≤ VW2 ≤ VDD.
Serial Input Register Clock Pin. Shifts in one bit at a time upon positive clock edges. VSCL ≤ (VDD + 0.3 V). Pull-up
resistor is recommended for SCL to ensure minimum power.
Digital Ground. Connect to system analog ground at a single point.
I2C Device Address 1. AD0 and AD1 allow four AD5253/AD5254 devices to be addressed.
A Terminal of RDAC3. VSS ≤ VA3 ≤ VDD.
B Terminal of RDAC3. VSS ≤ VB3 ≤ VDD.
Wiper Terminal of RDAC3. VSS ≤ VW3 ≤ VDD.
Positive Power Supply Pin. Connect +2.7 V to +5 V for single supply or ±2.7 V for dual supply, where VDD – VSS ≤ +5.5 V.
VDD must be able to source 35 mA for 26 ms when storing data to EEMEM.
Rev. B | Page 9 of 32
www.BDTIC.com/ADI
AD5253/AD5254
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
1.0
0.8
0.8
TA = –40°C, +25°C, +85°C, +125°C
0.6
0.4
0.2
0.2
DNL (LSB)
0.4
–0.2
0
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–0.8
–1.0
0
32
64
96
128
160
192
224
256
CODE (Decimal)
–1.0
0
32
64
128
160
192
224
256
CODE (Decimal)
Figure 3. R-INL vs. Code
Figure 6. DNL vs. Code
1.0
10
0.8
8
TA = –40°C, +25°C, +85°C, +125°C
0.6
6
0.4
4
0.2
2
IDD (μA)
0
IDD @ VDD = +5.5V
IDD @ VDD = +2.7V
0
–0.2
–2
–0.4
–4
–0.6
–6
–0.8
ISS @ VDD = +2.7V, VSS = –2.7V
–8
0
32
64
96
128
160
192
224
256
CODE (Decimal)
–10
–40
03824-0-016
–1.0
–20
0
20
40
60
80
100
03824-0-019
R-DNL (LSB)
96
03824-0-018
0
03824-0-015
R-INL (LSB)
0.6
TA = –40°C, +25°C, +85°C, +125°C
120
TEMPERATURE (°C)
Figure 4. R-DNL vs. Code
Figure 7. Supply Current vs. Temperature
1.0
10
0.8
TA = –40°C, +25°C, +85°C, +125°C
0.6
VDD = 5.5V
1
0.4
IDD (mA)
0
–0.2
0.1
0.01
–0.4
VDD = 2.7V
–0.6
0.001
–1.0
0
32
64
96
128
160
CODE (Decimal)
192
224
256
0.0001
Figure 5. INL vs. Code
0
1
2
3
4
5
6
DIGITAL INPUT VOLTAGE (V)
Figure 8. Supply Current vs. Digital Input Voltage, TA = 25°C
Rev. B | Page 10 of 32
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03824-0-020
–0.8
03824-0-017
INL (LSB)
0.2
AD5253/AD5254
240
30
200
POTENTIOMETER MODE TEMPCO (ppm/°C)
DATA = 0x00
VDD = 2.7V
TA = 25°C
180
RWB (Ω)
160
140
120
VDD = 5.5V
TA = 25°C
100
80
60
40
0
0
1
2
3
4
5
6
VBIAS (V)
20
15
10
5
03824-0-021
20
VDD = 5V
TA = –40°C/+85°C
VA = VDD
VB = 0V
25
0
0
32
64
96
128
160
192
224
256
CODE (Decimal)
Figure 12. Potentiometer Mode Tempco (∆VWB/VWB)/∆T × 106 vs. Code
Figure 9. Wiper Resistance vs. VBIAS
0
6
0xFF
–6
0x80
0x40
4
–12
0x20
–18
0x10
GAIN (dB)
2
ΔRWB (%)
03824-0-024
220
0
–2
–24
–30
0x08
–36
0x04
0x02
0x01
–42
0x00
–48
–4
0
20
40
60
80
100
120
TEMPERATURE (°C)
–60
10
1k
0
0x40
–18
GAIN (dB)
50
40
30
0x20
–24
0x10
–30
0x08
–36
0x04
–42
20
0x01
–48
10
0x00
0x02
0
64
96
128
160
192
224
256
CODE (Decimal)
03824-0-023
–54
32
10M
0x80
–12
60
0
1M
0xFF
–6
VDD = 5V
TA = –40°C/+85°C
VA = VDD
VB = 0V
70
100k
Figure 13. Gain vs. Frequency vs. Code, RAB = 1 kΩ, TA = 25°C
90
80
10k
FREQUENCY (Hz)
Figure 10. Change of RWB vs. Temperature
RHEOSTAT MODE TEMPCO (ppm/°C)
100
Figure 11. Rheostat Mode Tempco (∆RWB/RWB)/∆T × 106 vs. Code
–60
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 14. Gain vs. Frequency vs. Code, RAB = 10 kΩ, TA = 25°C
Rev. B | Page 11 of 32
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03824-0-026
–20
03824-0-022
–6
–40
03824-0-025
–54
AD5253/AD5254
0
1.2
0xFF
–6
TA = 25°C
0x80
1.0
–12
0x40
–18
0x10
–30
IDD (mA)
GAIN (dB)
0.8
0x20
–24
0x08
–36
0x04
–42
VDD = 5.5V
0.6
0.4
0x02
–48
0x01
VDD = 2.7V
0.2
–54
0x00
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
0
1
10
100
1k
10k
100k
1M
03824-0-030
10
03824-0-027
–60
10M
CLOCK FREQUENCY (Hz)
Figure 18. Supply Current vs. Digital Input Clock Frequency
Figure 15. Gain vs. Frequency vs. Code, RAB = 50 kΩ, TA = 25°C
0
0x80
VDD = 5V
0x40
–12
0x20
–18
GAIN (dB)
CLK
0xFF
–6
0x10
–24
0x08
–30
VW
0x04
–36
0x02
DIGITAL FEEDTHROUGH
–42
0x01
MIDSCALE TRANSITION
7FH ≥ 80H
–48
–54
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
400ns/DIV
03824-0-031
10
03824-0-028
0x00
–60
Figure 19. Clock Feedthrough and Midscale Transition Glitch
Figure 16. Gain vs. Frequency vs. Code, RAB = 100 kΩ, TA = 25°C
100
VDD = 5.5V
80
100kΩ
60
10kΩ
40
MIDSCALE
PRESET
1kΩ
0
–20
RESTORE RDAC3
SETTING TO 0xFF
50kΩ
MIDSCALE
PRESET
–40
–60
–100
0
32
64
96
128
160
192
CODE (Decimal)
224
256
Figure 17. ΔRAB vs. Code, TA = 25°C
VWB0
(0xFF
STORED
IN EEMEM)
VWB3
(0xFF
STORED
IN EEMEM)
03824-0-046
VDD = VA0 = VA3 = 3.3V
GND = VB0 = VB3
–80
03824-0-029
ΔRAB (Ω)
20
RESTORE RDAC0
SETTING TO 0xFF
VDD
(NO DECOUPLING
CAPS)
Figure 20. tEEMEM_RESTORE of RDAC0 and RDAC3
Rev. B | Page 12 of 32
www.BDTIC.com/ADI
AD5253/AD5254
6
RAB = 1kΩ
THEORETICAL IWB_MAX (mA)
VA = VB = OPEN
TA = 25°C
4
3
2
RAB = 10kΩ
1
RAB = 50kΩ
RAB = 100kΩ
0
0
8
16
24
32
RAB = 1kΩ
5
40
48
CODE (Decimal)
56
64
03824-0-033
THEORETICAL IWB_MAX (mA)
5
Figure 21. AD5253 IWB_MAX vs. Code
VA = VB = OPEN
TA = 25°C
4
3
2
RAB = 10kΩ
1
RAB = 50kΩ
RAB = 100kΩ
0
0
32
64
96
128
160
192
224
256
CODE (Decimal)
Figure 22. AD5254 IWB_MAX vs. Code
Rev. B | Page 13 of 32
www.BDTIC.com/ADI
03824-0-034
6
AD5253/AD5254
I2C INTERFACE
t8
t6
t2
t9
SCL
t4
t3
t2
t8
t7
t10
t5
t9
03824-0-003
SDA
t1
P
S
S
P
Figure 23. I2C Interface Timing Diagram
I2C INTERFACE GENERAL DESCRIPTION
From Master to Slave
From Slave to Master
S = start condition
P = stop condition
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
R/W = read enable at high; write enable at low
SLAVE ADDRESS
(7-BIT)
R/W
INSTRUCTIONS
(8-BIT)
A
DATA
(8-BIT)
A
A/A
P
A
P
03824-0-004
S
DATA TRANSFERRED
(N BYTES + ACKNOWLEDGE)
0 WRITE
Figure 24. I2C—Master Writing Data to Slave
SLAVE ADDRESS
(7-BIT)
R/W
DATA
(8-BIT)
A
DATA
(8-BIT)
A
03824-0-005
S
DATA TRANSFERRED
(N BYTES + ACKNOWLEDGE)
1 READ
Figure 25. I2C—Master Reading Data from Slave
SLAVE ADDRESS
(7-BIT)
R/W
A
READ OR WRITE
A/A
DATA
(N BYTES +
ACKNOWLEDGE)
S
SLAVE ADDRESS
REPEATED START
R/W
READ
OR WRITE
A
DATA
(N BYTES +
ACKNOWLEDGE)
A/A
P
03824-0-006
S
DIRECTION OF TRANSFER MAY
CHANGE AT THIS POINT
Figure 26. I2C—Combined Write/Read
Rev. B | Page 14 of 32
www.BDTIC.com/ADI
AD5253/AD5254
I2C INTERFACE DETAIL DESCRIPTION
From Master to Slave
From Slave to Master
S = start condition
P = stop condition
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
AD1, AD0 = I2C device address bits, must match with the logic states at Pins AD1, AD0
R/W= read enable bit at logic high; write enable bit at logic low
CMD/REG = command enable bit at logic high; register access bit at logic low
EE/RDAC = EEMEM register at logic high; RDAC register at logic low
A4, A3, A2, A1, A0 = RDAC/EEMEM register addresses
0
1
0
1
1
A
D
1
A
D
0
0
A
CMD/
REG
0
SLAVE ADDRESS
EE/
RDAC
A
4
A
3
A
2
A
1
INSTRUCTIONS
AND ADDRESS
0 WRITE
A
0
A
DATA
A/
A
(1 BYTE +
ACKNOWLEDGE)
P
03824-0-007
S
0 REG
Figure 27. Single Write Mode
0
1
0
1
1
A
D
1
A
D
0
0
A
CMD/
REG
SLAVE ADDRESS
0
EE/
RDAC
A
4
A
3
A
2
A
1
A
0
INSTRUCTIONS
AND ADDRESS
0 WRITE
A
RDAC_N
DATA
A
RDAC_N + 1
DATA
(N BYTE +
ACKNOWLEDGE)
A/
A
P
03824-0-008
S
0 REG
Figure 28. Consecutive Write Mode
Table 6. Addresses for Writing Data Byte Contents to RDAC Registers (R/W = 0, CMD/REG = 0, EE/RDAC = 0)
A4
0
0
0
0
0
:
:
0
A3
0
0
0
0
0
:
:
1
A2
0
0
0
0
1
:
:
1
A1
0
0
1
1
0
:
:
1
A0
0
1
0
1
0
:
:
1
RDAC
RDAC0
RDAC1
RDAC2
RDAC3
Reserved
:
:
Reserved
Data Byte Description
6-/8-bit wiper setting (2 MSB of AD5253 are X)
6-/8-bit wiper setting (2 MSB of AD5253 are X)
6-/8-bit wiper setting (2 MSB of AD5253 are X)
6-/8-bit wiper setting (2 MSB of AD5253 are X)
Rev. B | Page 15 of 32
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AD5253/AD5254
RDAC/EEMEM Write
Setting the wiper position requires an RDAC write operation.
The single write operation is shown in Figure 27, and the
consecutive write operation is shown in Figure 28. In the
consecutive write operation, if the RDAC is selected and the
address starts at 0, the first data byte goes to RDAC0, the second
data byte goes to RDAC1, the third data byte goes to RDAC2,
and the fourth data byte goes to RDAC3. This operation can be
continued for up to eight addresses with four unused addresses;
it then loops back to RDAC0. If the address starts at any of the
eight valid addresses, N, the data first goes to RDAC_N,
RDAC_N + 1, and so on; it loops back to RDAC0 after the
eighth address. The RDAC address is shown in Table 6.
Table 7. Addresses for Writing (Storing) RDAC Settings and
User-Defined Data to EEMEM Registers
(R/W = 0, CMD/REG = 0, EE/RDAC = 1)
While the RDAC wiper setting is controlled by a specific
RDAC register, each RDAC register corresponds to a specific
EEMEM location, which provides nonvolatile wiper storage
functionality. The addresses are shown in Table 7. The single
and consecutive write operations also apply to EEMEM write
operations.
There are 12 nonvolatile memory locations: EEMEM4 to
EEMEM15. Users can store 12 bytes of information, such as
memory data for other components, look-up tables, or system
identification information.
Table 8. Addresses for Reading (Restoring) RDAC Settings
and User Data from EEMEM
(R/W = 1, CMD/REG = 0, EE/RDAC = 1)
In a write operation to the EEMEM registers, the device disables
the I2C interface during the internal write cycle. Acknowledge
polling is required to determine the completion of the write
cycle. See the EEMEM Write-Acknowledge Polling section.
RDAC/EEMEM Read
The AD5253/AD5254 provide two different RDAC or EEMEM
read operations. For example, Figure 29 shows the method of
reading the RDAC0 to RDAC3 contents without specifying the
address, assuming Address RDAC0 was already selected in the
previous operation. If an RDAC_N address other than RDAC0
was previously selected, readback starts with Address N,
followed by N + 1, and so on.
Figure 30 illustrates a random RDAC or EEMEM read
operation. This operation allows users to specify which RDAC
or EEMEM register is read by issuing a dummy write command
to change the RDAC address pointer and then proceeding with
the RDAC read operation at the new address location.
A4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Data Byte Description
Store RDAC0 setting to EEMEM0 1
Store RDAC1 setting to EEMEM11
Store RDAC2 setting to EEMEM21
Store RDAC3 setting to EEMEM31
Store user data to EEMEM4
Store user data to EEMEM5
Store user data to EEMEM6
Store user data to EEMEM7
Store user data to EEMEM8
Store user data to EEMEM9
Store user data to EEMEM10
Store user data to EEMEM11
Store user data to EEMEM12
Store user data to EEMEM13
Store user data to EEMEM14
Store user data to EEMEM15
A4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Data Byte Description
Read RDAC0 setting from EEMEM0
Read RDAC1 setting from EEMEM1
Read RDAC2 setting from EEMEM2
Read RDAC3 setting from EEMEM3
Read User data from EEMEM4
Read user data from EEMEM5
Read user data from EEMEM6
Read user data from EEMEM7
Read user data from EEMEM8
Read user data from EEMEM9
Read user data from EEMEM10
Read user data from EEMEM11
Read user data from EEMEM12
Read user data from EEMEM13
Read user data from EEMEM14
Read user data from EEMEM15
Users can store any of the 64 RDAC settings for AD5253 or any of the 256
RDAC settings for the AD5254 directly to the EEMEM. This is not limited to
current RDAC wiper setting.
Rev. B | Page 16 of 32
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AD5253/AD5254
From Master to Slave
From Slave to Master
S = start condition
P = stop condition
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
AD1, AD0 = I2C device address bits, must match with the logic states at Pins AD1, AD0
R/W = read enable bit at logic high; write enable bit at logic low
CMD/REG = command enable bit at logic high; register access bit at logic low
C3, C2, C1, C0 = command bits
A2, A1, A0 = RDAC/EEMEM register addresses
0
1
0
1
1
A
D
1
A
D
0
1
A
RDAC_N OR EEMEM_N
REGISTER DATA
SLAVE ADDRESS
A
RDAC_N + 1 OR EEMEM_N + 1
REGISTER DATA
A
P
03824-0-009
S
(N BYTES + ACKNOWLEDGE)
1 READ
Figure 29. RDAC Current Read (Restricted to Previously Selected Address Stored in the Register)
0
A
INSTRUCTIONAL AND
ADDRESS
A
S
SLAVE ADDRESS
1
A
RDAC OR
EEMEM DATA
A/A
(N BYTES + ACKNOWLEDGE)
REPEATED START
0 WRITE
1 READ
P
03824-0-010
SLAVE ADDRESS
Figure 30. RDAC or EEMEM Random Read
S
0
1
0
1
1
A
D
1
A
D
0
0
A
CMD/
REG
C
3
C
2
C
1
C
0
A
2
A
1
RDAC SLAVE ADDRESS
0 WRITE
A
0
A
P
03824-0-011
S
1 CMD
Figure 31. RDAC Quick Command Write (Dummy Write)
Rev. B | Page 17 of 32
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AD5253/AD5254
RDAC/EEMEM Quick Commands
The AD5253/AD5254 feature 12 quick commands that facilitate
easy manipulation of RDAC wiper settings and provide RDACto-EEMEM storing and restoring functions. The command
format is shown in Figure 31, and the command descriptions
are shown in Table 9.
When using a quick command, issuing a third byte is not
needed, but is allowed. The quick commands reset and store
RDAC to EEMEM require acknowledge polling to determine
whether the command has finished executing.
bits are designated for the decimal portion of tolerance. As
shown in Table 10 and Figure 32, for example, if the rated RAB is
10 kΩ and the data readback from Address 11000 shows 0001
1100 and Address 11001 shows 0000 1111, then RDAC0
tolerance can be calculated as
MSB: 0 = +
Next 7 MSB: 001 1100 = 28
8 LSB: 0000 1111 = 15 × 2–8 = 0.06
Tolerance = 28.06% and, therefore,
RAB_ACTUAL = 12.806 kΩ
EEMEM Write-Acknowledge Polling
RAB Tolerance Stored in Read-Only Memory
The AD5253/AD5254 feature patented RAB tolerances storage in
the nonvolatile memory. The tolerance of each channel is stored
in the memory during the factory production and can be read
by users at any time. The knowledge of the stored tolerance,
which is the average of RAB over all codes (see Figure 16), allows
users to predict RAB accurately. This feature is valuable for
precision, rheostat mode, and open-loop applications, in which
knowledge of absolute resistance is critical.
The stored tolerances reside in the read-only memory and are
expressed as percentages. Each tolerance is 16 bits long and is
stored in two memory locations (see Table 10). The tolerance
data is expressed in sign magnitude binary format stored in two
bytes; an example is shown in Figure 32 . For the first byte in
Register N, the MSB is designated for the sign (0 = + and 1 = –)
and the 7 LSB is designated for the integer portion of the
tolerance. For the second byte in Register N + 1, all eight data
After each write operation to the EEMEM registers, an internal
write cycle begins. The I2C interface of the device is disabled. To
determine if the internal write cycle is complete and the I2C
interface is enabled, interface polling can be executed. I2C
interface polling can be conducted by sending a start condition
followed by the slave address and the write bit. If the I2C
interface responds with an ACK, the write cycle is complete and
the interface is ready to proceed with further operations. Otherwise, I2C interface polling can be repeated until it succeeds.
Command 2 and Command 7 also require acknowledge polling.
EEMEM Write Protection
Setting the WP pin to logic low after EEMEM programming
protects the memory and RDAC registers from future write
operations. In this mode, the EEMEM and RDAC read
operations function as normal.
Table 9. RDAC-to-EEMEM Interface and RDAC Operation Quick Command Bits (CMD/REG = 1, A2 = 0)
C3
0
0
0
0
0
0
0
0
1
1
1
1
1
:
:
1
1
C2
0
0
0
0
1
1
1
1
0
0
0
0
1
:
:
1
C1
0
0
1
1
0
0
1
1
0
0
1
1
0
:
:
1
C0
0
1
0
1
0
1
0
1
0
1
0
1
0
:
:
1
Command Description
NOP
Restore EEMEM (A1, A0) to RDAC (A1, A0) 1
Store RDAC (A1, A0) to EEMEM (A1, A0)
Decrement RDAC (A1, A0) 6 dB
Decrement all RDACs 6 dB
Decrement RDAC (A1, A0) one step
Decrement all RDACs one step
Reset: restore EEMEMs to all RDACs
Increment RDACs (A1, A0) 6 dB
Increment all RDACs 6 dB
Increment RDACs (A1, A0) one step
Increment all RDACs one step
Reserved
:
:
Reserved
This command leaves the device in the EEMEM read power state, which consumes power. Issue the NOP command to return the device to its idle state.
Rev. B | Page 18 of 32
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AD5253/AD5254
Table 10. Address Table for Reading Tolerance (CMD/REG = 0, EE/RDAC = 1, A4 = 1)
A3
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
A
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
Data Byte Description
Sign and 7-bit integer values of RDAC0 tolerance (read only)
8-bit decimal value of RDAC0 tolerance (read only)
Sign and 7-bit integer values of RDAC1 tolerance (read only)
8-bit decimal value of RDAC1 tolerance (read only)
Sign and 7-bit integer values of RDAC2 tolerance (read only)
8-bit decimal value of RDAC2 tolerance (read only)
Sign and 7-bit integer values of RDAC3 tolerance (read only)
8-bit decimal value of RDAC3 tolerance (read only)
D7
D6
D5
D4
D3
D2
D1
D0
SIGN
26
25
24
23
22
21
20
SIGN
A
D7
D6
D5
D4
D3
D2
D1
D0
2–1
2–2
2–3
2–4
2–5
2–6
2–7
2–8
7 BITS FOR INTEGER NUMBER
8 BITS FOR DECIMAL NUMBER
A
03824-0-012
A4
1
1
1
1
1
1
1
1
Figure 32. Format of Stored Tolerance in Sign Magnitude Format with Bit Position Descriptions (Unit is Percent, Only Data Bytes Are Shown)
Rev. B | Page 19 of 32
www.BDTIC.com/ADI
AD5253/AD5254
I2C-COMPATIBLE 2-WIRE SERIAL BUS
1
9
9
1
9
1
SDA
START BY
MASTER
0
1
0
1
X
1 AD1 AD0 R/W
ACK. BY
AD525x
X
X
X
X
X
X
X
D7 D6
ACK. BY
AD525x
D5
D3
D2
D1
D0
ACK. BY
AD525x
STOP BY
MASTER
FRAME 1
DATA BYTE
FRAME 2
INSTRUCTION BYTE
FRAME 1
SLAVE ADDRESS BYTE
D4
03824-0-013
SCL
Figure 33. General I2C Write Pattern
1
9
1
9
SCL
0
1
0
1
1
AD1 AD0 R/W
D7
D6
D5
D4
D3
D1
D2
ACK. BY
AD525x
START BY
MASTER
D0
NO ACK. BY
MASTER
FRAME1
SLAVE ADDRESS BYTE
FRAME 2
RDAC REGISTER
STOP BY
MASTER
03824-0-014
SDA
Figure 34. General I2C Read Pattern
the addresses of the EEMEM and RDAC registers (see
Figure 27 and Figure 28). When MSB = 1 or when the
device is in CMD mode, the four bits following the MSB
are C3 to C1, which correspond to 12 predefined EEMEM
controls and quick commands; there are also four factoryreserved commands. The 3 LSB—A2, A1, and A0—are 4channel RDAC addresses (see Figure 31). After
acknowledging the instruction byte, the last byte in the
write mode is the data byte. Data is transmitted over the
serial bus in sequences of nine clock pulses (eight data bits
followed by an acknowledge bit). The transitions on the
SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see Figure 33).
The first byte of the AD5253/AD5254 is a slave address byte
(see Figure 33 and Figure 34). It has a 7-bit slave address and an
R/W bit. The 5 MSB of the slave address is 01011, and the next
2 LSB is determined by the states of the AD1 and AD0 pins.
AD1 and AD0 allow the user to place up to four
AD5253/AD5254 devices on one bus.
AD5253/AD5254 can be controlled via an I2C-compatible serial
bus and are connected to this bus as slave devices. The 2-wire
I2C serial bus protocol (see Figure 33 and Figure 34) follows:
1.
The master initiates a data transfer by establishing a start
condition, such that SDA goes from high to low while SCL
is high (see Figure 33). The following byte is the slave
address byte, which consists of the 5 MSB of a slave address
defined as 01011. The next two bits are AD1 and AD0, I2C
device address bits. Depending on the states of their AD1
and AD0 bits, four AD5253/AD5254 devices can be
addressed on the same bus. The last LSB, the R/W bit,
determines whether data is read from or written to the
slave device.
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is called an acknowledge bit). At
this stage, all other devices on the bus remain idle while
the selected device waits for data to be written to or read
from its serial register.
2.
3.
In current read mode, the RDAC0 data byte immediately
follows the acknowledgment of the slave address byte.
After an acknowledgement, RDAC1 follows, then RDAC2,
and so on. (There is a slight difference in write mode,
where the last eight data bits representing RDAC3 data are
followed by a no acknowledge bit.) Similarly, the
transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of
SCL (see Figure 34). Another reading method, random
read method, is shown in Figure 30.
4.
When all data bits have been read or written, a stop
condition is established by the master. A stop condition is
defined as a low-to-high transition on the SDA line that
occurs while SCL is high. In write mode, the master pulls
the SDA line high during the 10th clock pulse to establish a
stop condition (see Figure 33). In read mode, the master
issues a no acknowledge for the ninth clock pulse, that is,
the SDA line remains high. The master brings the SDA line
low before the 10th clock pulse and then brings the SDA
line high to establish a stop condition (see Figure 34).
In the write mode (except when restoring EEMEM to the
RDAC register), there is an instruction byte that follows
the slave address byte. The MSB of the instruction byte is
labeled CMD/REG. MSB = 1 enables CMD, the command
instruction byte; MSB = 0 enables general register writing.
The third MSB in the instruction byte, labeled EE/RDAC,
is true when MSB = 0 or when the device is in general
writing mode. EE enables the EEMEM register, and REG
enables the RDAC register. The 5 LSB, A4 to A0, designates
Rev. B | Page 20 of 32
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AD5253/AD5254
THEORY OF OPERATION
The AD5253/AD5254 are quad-channel digital potentiometers
in 1 kΩ, 10 kΩ, 50 kΩ, or 100 kΩ that allow 64/256 linear resistance step adjustments. The AD5253/AD5254 employ doublegate CMOS EEPROM technology, which allows resistance
settings and user-defined data to be stored in the EEMEM
registers. The EEMEM is nonvolatile, such that settings remain
when power is removed. The RDAC wiper settings are restored
from the nonvolatile memory settings during device power-up
and can also be restored at any time during operation.
The AD5253/AD5254 resistor wiper positions are determined
by the RDAC register contents. The RDAC register acts like a
scratch-pad register, allowing unlimited changes of resistance
settings. RDAC register contents can be changed using the
device’s serial I2C interface. The format of the data-words and
the commands to program the RDAC registers are discussed in
the I2C Interface section.
The four RDAC registers have corresponding EEMEM memory
locations that provide nonvolatile storage of resistor wiper
position settings. The AD5253/AD5254 provide commands to
store the RDAC register contents to their respective EEMEM
memory locations. During subsequent power-on sequences, the
RDAC registers are automatically loaded with the stored value.
Whenever the EEMEM write operation is enabled, the device
activates the internal charge pump and raises the EEMEM cell
gate bias voltage to a high level; this essentially erases the
current content in the EEMEM register and allows subsequent
storage of the new content. Saving data to an EEMEM register
consumes about 35 mA of current and lasts approximately
26 ms. Because of charge-pump operation, all RDAC channels
may experience noise coupling during the EEMEM writing
operation.
The EEMEM restore time in power-up or during operation is
about 300 μs. Note that the power-up EEMEM refresh time
depends on how fast VDD reaches its final value. As a result, any
supply voltage decoupling capacitors limit the EEMEM restore
time during power-up. For example, Figure 20 shows the
power-up profile of the VDD where there is no decoupling
capacitors and the applied power is a digital signal. The device
initially resets the RDACs to midscale before restoring the
EEMEM contents. The omission of the decoupling capacitors
should only be considered when the fast restoring time is
absolutely needed in the application. In addition, users should
issue a NOP Command 0 immediately after using Command 1
to restore the EEMEM setting to RDAC, thereby minimizing
supply current dissipation. Reading user data directly from
EEMEM does not require a similar NOP command execution.
Table 11. Quick Commands
Command
0
1
2
3
4
5
6
7
8
9
10
11
12 to 15
Description
NOP.
Restore EEMEM content to RDAC. User should
issue NOP immediately after this command to
conserve power.
Store RDAC register setting to EEMEM.
Decrement RDAC 6 dB (shift data bits right).
Decrement all RDACs 6 dB (shift all data bits right).
Decrement RDAC one step.
Decrement all RDACs one step.
Reset EEMEM contents to all RDACs.
Increment RDAC 6 dB (shift data bits left).
Increment all RDACs 6 dB (shift all data bits left).
Increment RDAC one step.
Increment all RDACs one step.
Reserved.
LINEAR INCREMENT/DECREMENT COMMANDS
The increment and decrement commands (10, 11, 5, and 6) are
useful for linear step-adjustment applications. These commands
simplify microcontroller software coding by allowing the
controller to send just an increment or decrement command to
the AD5253/AD5254. The adjustments can be directed to a
single RDAC or to all four RDACs.
±6 dB ADJUSTMENTS
(DOUBLING/HALVING WIPER SETTING)
The AD5253/AD5254 accommodate ±6 dB adjustments of the
RDAC wiper positions by shifting the register contents to left/
right for increment/decrement operations, respectively. Command 3, Command 4, Command 8, and Command 9 can be
used to increment or decrement the wiper positions in 6 dB
steps synchronously or asynchronously.
Incrementing the wiper position by +6 dB essentially doubles
the RDAC register value, whereas decrementing the wiper
position by –6 dB halves the register content. Internally, the
AD5253/AD5254 use shift registers to shift the bits left and
right to achieve a ±6 dB increment or decrement. The
maximum number of adjustments is nine and eight steps for
incrementing from zero scale and decrementing from full scale,
respectively. These functions are useful for various audio/video
level adjustments, especially for white LED brightness settings
in which human visual responses are more sensitive to large
adjustments than to small adjustments.
In addition to the movement of data between RDAC and
EEMEM registers, the AD5253/AD5254 provide other shortcut
commands that facilitate programming, as shown in Table 11.
Rev. B | Page 21 of 32
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AD5253/AD5254
DIGITAL INPUT/OUTPUT CONFIGURATION
MULTIPLE DEVICES ON ONE BUS
SDA is a digital input/output with an open-drain MOSFET that
requires a pull-up resistor for proper communication. On the
other hand, SCL and WP are digital inputs for which pull-up
resistors are recommended to minimize the MOSFET crossconduction current when the driving signals are lower than
VDD. SCL and WP have ESD protection diodes, as shown in
Figure 35 and Figure 36.
The AD5253/AD5254 are equipped with two addressing pins,
AD1 and AD0, that allow up to four AD5253/AD5254 devices
to be operated on one I2C bus. To achieve this result, the states of
AD1 and AD0 on each device must first be defined. An example
is shown in Table 12 and Figure 37. In I2C programming, each
device is issued a different slave address—01011(AD1)(AD0)—
to complete the addressing.
WP can be permanently tied to VDD without a pull-up resistor if
the write-protect feature is not used. If WP is left floating, an
internal current source pulls it low to enable write protection. In
applications in which the device is programmed infrequently,
this allows the part to default to write-protection mode after
any one-time factory programming or field calibration without
using an on-board pull-down resistor. Because there are
protection diodes on all inputs, the signal levels must not be
greater than VDD to prevent forward biasing of the diodes.
Table 12. Multiple Devices Addressing
AD1
0
0
1
1
AD0
0
1
0
1
Device Addressed
U1
U2
U3
U4
5V
RP
RP
SDA
VDD
MASTER
SCL
SDA
SCL
AD1
SCL
AD0
03824-0-035
AD5253/
AD5254
5V
SDA
SCL
AD1
AD0
AD5253/
AD5254
5V
SDA
SCL
AD1
AD0
AD5253/
AD5254
SDA
SCL
AD1
AD0
AD5253/
AD5254
03824-0-037
5V
Figure 37. Multiple AD5253/AD5254 Devices on a Single Bus
GND
Figure 35. SCL Digital Input
VDD
INPUTS
03824-0-036
WP
GND
Figure 36. Equivalent WP Digital Input
In wireless base station smart-antenna systems that require
arrays of digital potentiometers to bias the power amplifiers,
large numbers of AD5253/AD5254 devices can be addressed by
using extra decoders, switches, and I/O buses, as shown in
Figure 38. For example, to communicate to a total of 16 devices,
four decoders and 16 sets of combinational switches (four sets
shown in Figure 38) are needed. Two I/O buses serve as the
common inputs of the four 2 × 4 decoders and select four sets
of outputs at each combination. Because the four sets of
combination switch outputs are unique, as shown in Figure 38,
a specific device is addressed by properly programming the I2C
with the slave address defined as 01011(AD1)(AD0). This
operation allows one of 16 devices to be addressed, provided
that the inputs of the two decoders do not change states. The
inputs of the decoders are allowed to change once the operation
of the specified device is completed.
Rev. B | Page 22 of 32
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AD5253/AD5254
VDD
+5V
×4
R1
2
2×4
DECODER
4
N1
AD1
A
AD0
W
B
×4
R2X
VSS
AD1
2×4
DECODER
4
03824-0-039
+5V
Figure 39. Maximum Terminal Voltages Set by VDD and VSS
N2X
+5
POWER-UP AND POWER-DOWN SEQUENCES
P2Y
Because the ESD protection diodes limit the voltage compliance
at Terminal A, Terminal B, and Terminal W (Figure 39), it is
important to power VDD/VSS before applying any voltage to
these terminals. Otherwise, the diodes are forward biased such
that VDD/VSS are powered unintentionally and may affect the
user’s circuit. Similarly, VDD/VSS should be powered down last.
The ideal power-up sequence is in the following order: GND,
VDD, VSS, digital inputs, and VA/VB/VW. The order of powering
VA, VB, VW, and the digital inputs is not important, as long as
they are powered after VDD/VSS.
AD0
P2Y
+5V
4
×4
P3X
AD1
R3X
R3Y
AD0
N3Y
2×4
DECODER
LAYOUT AND POWER SUPPLY BIASING
It is always a good practice to employ a compact, minimum
lead-length layout design. The leads to the input should be as
direct as possible, with a minimum conductor length. Ground
paths should have low resistance and low inductance.
+5V
4
×4
P4
AD1
AD0
03824-0-038
R4
Figure 38. Four Devices with AD1 and AD0 of 00
Similarly, it is also good practice to bypass the power supplies
with quality capacitors. Low equivalent series resistance (ESR)
1 μF to 10 μF tantalum or electrolytic capacitors should be
applied at the supplies to minimize any transient disturbance
and filter low frequency ripple. Figure 40 illustrates the basic
supply-bypassing configuration for the AD5253/AD5254.
TERMINAL VOLTAGE OPERATION RANGE
AD5253/AD5254
The AD5253/AD5254 are designed with internal ESD diodes
for protection; these diodes also set the boundaries for the
terminal operating voltages. Positive signals present on
Terminal A, Terminal B, or Terminal W that exceed VDD are
clamped by the forward-biased diode. Similarly, negative signals
on Terminal A, Terminal B, or Terminal W that are more
negative than VSS are also clamped (see Figure 39). In practice,
users should not operate VAB, VWA, and VWB to be higher than
the voltage across VDD to VSS, but VAB, VWA, and VWB have no
polarity constraint.
VDD
C3
10μF
C4
VSS
VDD
C1
0.1μF
C2
10μF
0.1μF
VSS
GND
03824-0-040
2×4
DECODER
Figure 40. Power Supply-Bypassing Configuration
The ground pin of the AD5253/AD5254 is used primarily as a
digital ground reference. To minimize the digital ground
bounce, the AD5253/AD5254 ground terminal should be joined
remotely to the common ground (see Figure 40).
Rev. B | Page 23 of 32
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AD5253/AD5254
DIGITAL POTENTIOMETER OPERATION
PROGRAMMABLE RHEOSTAT OPERATION
The structure of the RDAC is designed to emulate the
performance of a mechanical potentiometer. The RDAC
contains a string of resistor segments with an array of analog
switches that act as the wiper connection to the resistor array.
The number of points is the resolution of the device. For
example, the AD5253/AD5254 emulate 64/256 connection
points with 64/256 equal resistance, RS, allowing them to
provide better than 1.5%/0.4% resolution.
If either the W-to-B or W-to-A terminal is used as a variable
resistor, the unused terminal can be opened or shorted with W;
such operation is called rheostat mode (see Figure 42). The
resistance tolerance can range ±20%.
W
B
Figure 41 provides an equivalent diagram of the connections
between the three terminals that make up one channel of the
RDAC. Switches SWA and SWB are always on, but only one of
switches SW(0) to SW(2N–1) can be on at a time (determined by
the setting decoded from the data bit). Because the switches are
nonideal, there is a 75 Ω wiper resistance, RW. Wiper resistance
is a function of supply voltage and temperature: Lower supply
voltages and higher temperatures result in higher wiper
resistances. Consideration of wiper resistance dynamics is
important in applications in which accurate prediction of
output resistance is required.
SWA
AX
SW (2N – 1)
RDAC
WIPER
REGISTER
AND
DECODER
W
B
W
B
Figure 42. Rheostat Mode Configuration
The nominal resistance of the AD5253/AD5254 has 64/256
contact points accessed by the wiper terminal, plus the B
terminal contact. The 6-/8-bit data-word in the RDAC register
is decoded to select one of the 64/256 settings. The wiper’s first
connection starts at the B terminal for Data 0x00. This B terminal connection has a wiper contact resistance, RW, of 75 Ω,
regardless of the nominal resistance. The second connection
(the AD5253 10 kΩ part) is the first tap point where RWB = 231 Ω
(RWB = RAB/64 + RW = 156 Ω + 75 Ω) for Data 0x01, and so on.
Each LSB data value increase moves the wiper up the resistor
ladder until the last tap point is reached at RWB = 9893 Ω. See
Figure 41 for a simplified diagram of the equivalent RDAC circuit.
SW (2N – 2)
AD5253: RWB(D) = (D/64) × RAB + 75 Ω
(1)
AD5254: RWB(D) = (D/256) × RAB + 75 Ω
(2)
where:
D is the decimal equivalent of the data contained in the
RDAC latch.
RAB is the nominal end-to-end resistance.
RS
SW(1)
RS
A
The general equation that determines the digitally programmed
output resistance between W and B is
WX
RS
A
03824-0-042
A
SW(0)
DIGITAL
CIRCUITRY
OMIITTED FOR
CLARITY
SWB
BX
03824-0-041
RS = RAB/2N
Figure 41. Equivalent RDAC Structure
Rev. B | Page 24 of 32
www.BDTIC.com/ADI
AD5253/AD5254
PROGRAMMABLE POTENTIOMETER OPERATION
100
RWA
If all three terminals are used, the operation is called potentiometer mode (see Figure 44); the most common configuration
is the voltage divider operation.
RWB
VI
A
50
VC
W
B
25
03824-0-044
RAB (%)
75
Figure 44. Potentiometer Mode Configuration
0
10
32
48
63
D (Code in Decimal)
03824-0-043
If the wiper resistance is ignored, the transfer function is simply
0
AD5253: VW =
D
× V AB + V B
64
(5)
AD5254: VW =
D
× V AB + V B
256
(6)
Figure 43. AD5253 RWA(D) and RWB(D) vs. Decimal Code
Since the digital potentiometer is not ideal, a 75 Ω finite wiper
resistance is present that can easily be seen when the device is
programmed at zero scale. Because of the fine geometric and
interconnects employed by the device, care should be taken to
limit the current conduction between W and B to no more than
±5 mA continuous for a total resistance of 1 kΩ or a pulse of
±20 mA to avoid degradation or possible destruction of the
device. The maximum dc current for AD5253 and AD5254 are
shown in Figure 21 and Figure 22, respectively.
where 2N is the number of steps.
Similar to the mechanical potentiometer, the resistance of the
RDAC between Wiper W and Terminal A also produces a
digitally controlled complementary resistance, RWA. When these
terminals are used, the B terminal can be opened. The RWA
starts at a maximum value and decreases as the data loaded into
the latch increases in value (see Figure 43. The general equation
for this operation is
Unlike in rheostat mode operation, where the tolerance is high,
potentiometer mode operation yields an almost ratiometric
function of D/2N with a relatively small error contributed by the
RW terms. Therefore, the tolerance effect is almost cancelled.
Similarly, the ratiometric adjustment also reduces the
temperature coefficient effect to 50 ppm/°C, except at low value
codes where RW dominates.
AD5253: RWA(D) = [(64 – D)/64] × RAB + 75 Ω
(3)
AD5254: RWA(D) = [(256 – D)/256] × RAB + 75 Ω
(4)
The typical distribution of RAB from channel-to-channel
matches is about ±0.15% within a given device. On the other
hand, device-to-device matching is process-lot dependent with
a ±20% tolerance.
A more accurate calculation that includes the wiper resistance
effect is
D
R AB + RW
N
VW (D) = 2
VA
R AB + 2RW
(7)
Potentiometer mode operations include other applications such
as op amp input, feedback-resistor networks, and other voltagescaling applications. The A, W, and B terminals can, in fact, be
input or output terminals, provided that |VA|, |VW|, and |VB| do
not exceed VDD to VSS.
Rev. B | Page 25 of 32
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AD5253/AD5254
APPLICATIONS INFORMATION
RGB LED BACKLIGHT CONTROLLER
FOR LCD PANELS
Because high power (>1 W) RGB LEDs offer superior color
quality compared with cold cathode florescent lamps (CCFLs)
as backlighting sources, it is likely that high-end LCD panels
will employ RGB LEDs as backlight in the near future. Unlike
conventional LEDs, high power LEDs have a forward voltage of
2 V to 4 V and consume more than 350 mA at maximum
brightness. The LED brightness is a linear function of the
conduction current, but not of the forward voltage. To increase
the brightness of a given color, multiple LEDs can be connected
in series, rather than in parallel, to achieve uniform brightness.
For example, three red LEDs configured in series require an
average of 6 V to 12 V headroom, but the circuit operation
requires current control. As a result, Figure 45 shows the
implementation of one high power RGB LED controller using a
AD5254, a boost regulator, an op amp, and power MOSFETs.
The ADP1610 (U2 in Figure 45) is an adjustable boost regulator
with its output adjusted by the AD5254’s RDAC3. Such an
output should be set high enough for proper operation but low
enough to conserve power. The ADP1610’s 1.2 V band gap
reference is buffered to provide the reference level for the
voltage dividers set by the AD5254’s RDAC0 to RDAC2 and
Resistor R2 to Resistor R4. For example, by adjusting the
AD5254’s RDAC0, the desirable voltage appears across the
sense resistors, RR. If U2’s output is set properly, op amp U3A
and power MOSFET N1 do whatever is necessary to regulate
the current of the loop. As a result, the current through the
sense resistor and the red LEDs is
IR =
V RR
RR
(8)
R8 is needed to prevent oscillation.
In addition to the 256 levels of adjustable current/brightness,
users can also apply a PWM signal at U3’s SD pin to achieve
finer brightness resolution or better power efficiency.
Rev. B | Page 26 of 32
www.BDTIC.com/ADI
AD5253/AD5254
+5V
C10
10μF
U1
U2
R1
R5
VDD
R6
C1
0.1μF
R7
RDAC3
22kΩ 22kΩ
SCL
SDA
U3D
10kΩ
B3
CLK
SDI
RC
VREF = 2.5V
AD8594
R4
10kΩ 10kΩ
A3
R3
R2
100kΩ
CC
AD5254
250kΩ 250kΩ 250kΩ
390μF
IN
10μF
L1
ADP1610
D1
SW
FB
SD
COMP
SS RT GND
10μF
+5V
CSS 10μF
DB1
DG1
DR1
DB2
DG2
DR2
DB3
DG3
DR3
C11
8
A2
W2
RDAC2
VOUT
C3
VB
0.1μF
IB
N3
U3C
V+
AD8594
V–
4
10kΩ B2
R10
4.7Ω
IRFL3103
IG
VRB
VG
A1
U3B
RB
W1
RDAC1
0.1Ω
N2
R9
10kΩ B1
AD8594
IRFL3103
4.7Ω
A0
RDAC0
W0
VRG
0.1Ω
VR
N1
R8
10kΩ B0
AD8594
4.7Ω
IRFL3103
VSS GND AD0 AD1
VRR
RR
PWM
SD
0.1Ω
03824-0-045
L1 - SLF6025-100M1R0
D1 - MBR0520LT1
RG
U3A
IR
Figure 45. Digital Potentiometer-Based RGB LED Controller
Rev. B | Page 27 of 32
www.BDTIC.com/ADI
AD5253/AD5254
OUTLINE DIMENSIONS
6.60
6.50
6.40
20
11
4.50
4.40
4.30
6.40 BSC
1
10
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
COPLANARITY
0.10
0.30
0.19
0.20
0.09
SEATING
PLANE
0.75
0.60
0.45
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AC
Figure 46. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
Rev. B | Page 28 of 32
www.BDTIC.com/ADI
AD5253/AD5254
ORDERING GUIDE
Model 1
AD5253BRU1
AD5253BRU1-RL7
AD5253BRUZ1 2
AD5253BRUZ1-RL72
AD5253BRU10
AD5253BRU10-RL7
AD5253BRUZ102
AD5253BRUZ10-RL72
AD5253BRU50
AD5253BRU50-RL7
AD5253BRUZ502
AD5253BRUZ50-RL72
AD5253BRU100
AD5253BRU100-RL7
AD5253BRUZ1002
AD5253BRUZ100-RL72
AD5253EVAL
AD5254BRU1
AD5254BRU1-RL7
AD5254BRUZ12
AD5254BRUZ1-RL72
AD5254BRU10
AD5254BRU10-RL7
AD5254BRUZ102
AD5254BRUZ10-RL72
AD5254BRU50
AD5254BRU50-RL7
AD5254BRUZ502
AD5254BRUZ50-RL72
AD5254BRU100
AD5254BRU100-RL7
AD5254BRUZ1002
AD5254BRUZ100-RL72
EVAL-AD5254EBZ2
Step
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
RAB (kΩ)
1
1
1
1
10
10
10
10
50
50
50
50
100
100
100
100
10
1
1
1
1
10
10
10
10
50
50
50
50
100
100
100
100
10
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
Evaluation Board
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
Evaluation Board
Package
Option
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
Ordering
Quantity
75
1,000
75
1,000
75
1,000
75
1,000
75
1,000
75
1,000
75
1,000
75
1,000
1
75
1,000
75
1,000
75
1,000
75
1,000
75
1,000
75
1,000
75
1,000
75
1,000
1
1
In the package marking, Line 1 shows the part number. Line 2 shows the branding information, such that B1 = 1 kΩ, B10 = 10 kΩ, and so on. There is also a
“#” marking for the Pb-free part. Line 3 shows the date code in YYWW.
2
Z = RoHS Compliant Part.
Rev. B | Page 29 of 32
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AD5253/AD5254
NOTES
Rev. B | Page 30 of 32
www.BDTIC.com/ADI
AD5253/AD5254
NOTES
Rev. B | Page 31 of 32
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AD5253/AD5254
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
© 2003–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03824-0-10/09(B)
Rev. B | Page 32 of 32
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