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AD2S1210 数据手册DataSheet下载

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AD2S1210 数据手册DataSheet下载
Variable Resolution, 10-Bit to 16-Bit R/D
Converter with Reference Oscillator
AD2S1210
FEATURES
DC and ac servo motor control
Encoder emulation
Electric power steering
Electric vehicles
Integrated starter generators/alternators
Automotive motion sensing and control
REFERENCE
OSCILLATOR
(DAC)
EXCITATION
OUTPUTS
REFERENCE
PINS
CRYSTAL
VOLTAGE
REFERENCE
INTERNAL
CLOCK
GENERATOR
SYNTHETIC
REFERENCE
AD2S1210
ADC
INPUTS
FROM
RESOLVER
TYPE II
TRACKING LOOP
FAULT
DETECTION
ADC
POSITION
REGISTER
ENCODER
EMULATION
OUTPUTS
VELOCITY
REGISTER
CONFIGURATION
REGISTER
DATA I/O
MULTIPLEXER
DATA BUS OUTPUT
www.BDTIC.com/ADI
DATA I/O
RESET
Figure 1.
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD2S1210 is a complete 10-bit to 16-bit resolution tracking
resolver-to-digital converter, integrating an on-board programmable sinusoidal oscillator that provides sine wave excitation
for resolvers.
1.
The converter accepts 3.15 V p-p ± 27% input signals, in the range
of 2 kHz to 20 kHz on the sine and cosine inputs. A Type II
servo loop is employed to track the inputs and convert the input
sine and cosine information into a digital representation of the
input angle and velocity. The maximum tracking rate is 3125 rps.
FAULT
DETECTION
OUTPUTS
07467-001
APPLICATIONS
FUNCTIONAL BLOCK DIAGRAM
ENCODER
EMULATION
Complete monolithic resolver-to-digital converter
3125 rps maximum tracking rate (10-bit resolution)
±2.5 arc minutes of accuracy
10-/12-/14-/16-bit resolution, set by user
Parallel and serial 10-bit to 16-bit data ports
Absolute position and velocity outputs
System fault detection
Programmable fault detection thresholds
Differential inputs
Incremental encoder emulation
Programmable sinusoidal oscillator on-board
Compatible with DSP and SPI interface standards
5 V supply with 2.3 V to 5 V logic interface
−40°C to +125°C temperature rating
2.
3.
4.
5.
6.
Ratiometric tracking conversion. The Type II tracking loop
provides continuous output position data without
conversion delay. It also provides noise immunity and
tolerance of harmonic distortion on the reference and
input signals.
System fault detection. A fault detection circuit can sense
loss of resolver signals, out-of-range input signals, input
signal mismatch, or loss of position tracking. The fault
detection threshold levels can be individually programmed
by the user for optimization within a particular application.
Input signal range. The sine and cosine inputs can accept
differential input voltages of 3.15 V p-p ± 27%.
Programmable excitation frequency. Excitation frequency
is easily programmable to a number of standard frequencies
between 2 kHz and 20 kHz.
Triple format position data. Absolute 10-bit to 16-bit angular
position data is accessed via either a 16-bit parallel port or a
4-wire serial interface. Incremental encoder emulation is in
standard A-quad-B format with direction output available.
Digital velocity output. 10-bit to 16-bit signed digital velocity
accessed via either a 16-bit parallel port or a 4-wire serial
interface.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
AD2S1210
TABLE OF CONTENTS
Features .............................................................................................. 1 LOS Threshold Register ............................................................ 21 Applications ....................................................................................... 1 DOS Overrange Threshold Register ........................................ 21 Functional Block Diagram .............................................................. 1 DOS Mismatch Threshold Register ......................................... 21 General Description ......................................................................... 1 DOS Reset Maximum and Minimum Threshold Registers . 22 Product Highlights ........................................................................... 1 LOT High Threshold Register .................................................. 22 Revision History ............................................................................... 2 LOT Low Threshold Register ................................................... 22 Specifications..................................................................................... 3 Excitation Frequency Register .................................................. 22 Timing Specifications .................................................................. 6 Control Register ......................................................................... 22 Absolute Maximum Ratings............................................................ 8 Software Reset Register ............................................................. 23 ESD Caution .................................................................................. 8 Fault Register .............................................................................. 23 Pin Configuration and Function Descriptions ............................. 9 Digital interface .............................................................................. 24 Typical Performance Characteristics ........................................... 11 SOE Input .................................................................................... 24 Resolver Format Signals................................................................. 15 SAMPLE Input............................................................................ 24 Theory of Operation ...................................................................... 16 Data Format ................................................................................ 24 Resolver to Digital Conversion ................................................. 16 Parallel Interface ......................................................................... 24 Fault Detection Circuit .............................................................. 16 Serial Interface ............................................................................ 28 On-Board Programmable Sinusoidal Oscillator .................... 18 Incremental Encoder Outputs .................................................. 31 www.BDTIC.com/ADI
Synthetic Reference Generation ............................................... 18 Supply Sequencing and Reset ................................................... 31 Configuration of AD2S1210 ......................................................... 20 Circuit Dynamics ........................................................................... 32 Modes of Operation ................................................................... 20 Loop Response Model ............................................................... 32 Register Map.................................................................................... 21 Sources of Error .......................................................................... 33 Position Register ......................................................................... 21 Outline Dimensions ....................................................................... 34 Velocity Register ......................................................................... 21 Ordering Guide .......................................................................... 34 REVISION HISTORY
8/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 36
AD2S1210
SPECIFICATIONS
AVDD = DVDD = 5.0 V ± 5%, CLKIN = 8.192 MHz ± 25%, EXC, EXC frequency = 10 kHz to 20 kHz (10-bit); 6 kHz to 20 kHz (12-bit);
3 kHz to 12 kHz (14-bit); 2 kHz to 10 kHz (16-bit); TA = TMIN to TMAX; unless otherwise noted.1
Table 1.
Parameter
SINE, COSINE INPUTS2
Voltage Amplitude
Input Bias Current
Input Impedance
Phase Lock Range
Common-Mode Rejection
ANGULAR ACCURACY3
Angular Accuracy
Min
Typ
Max
Unit
Conditions/Comments
2.3
3.15
4.0
V p-p
8.25
μA
kΩ
Degrees
arc sec/V
Sinusoidal waveforms, differential SIN to SINLO,
COS to COSLO
VIN = 4.0 V p-p, CLKIN = 8.192 MHz
VIN = 4.0 V p-p, CLKIN = 8.192 MHz
Sine/cosine vs. EXC output, Control Register D3 = 0
10 Hz to 1 MHz, Control Register D4 = 0
±5 + 1 LSB
±10 + 1 LSB
arc min
arc min
Bits
B, D grades
A, C grades
No missing codes
±1
±2
±2
±4
±4
±8
±16
±32
±0.9
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
B, D grades
A, C grades
B, D grades
A, C grades
B, D grades
A, C grades
B, D grades
A, C grades
±2
±4
±2
±4
±4
±8
±16
±32
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Bits
B, D grades, zero acceleration
A, C grades, zero acceleration
B, D grades, zero acceleration
A, C grades, zero acceleration
B, D grades, zero acceleration
A, C grades, zero acceleration
B, D grades, zero acceleration
A, C grades, zero acceleration
6500
5300
2800
2200
1500
1200
350
275
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
485
−44
+44
±20
±2.5 + 1 LSB
±5 + 1 LSB
10, 12, 14, 16
Resolution
Linearity INL
10-bit
12-bit
14-bit
16-bit
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Linearity DNL
Repeatability
VELOCITY OUTPUT
Velocity Accuracy4
10-bit
±1
12-bit
14-bit
16-bit
Resolution5
DYNAMNIC PERFORMANCE
Bandwidth
10-bit
12-bit
14-bit
16-bit
9, 11, 13, 15
2000
2900
900
1200
400
600
100
125
Rev. 0 | Page 3 of 36
CLKIN = 8.192 MHz
CLKIN = 8.192 MHz
CLKIN = 8.192 MHz
CLKIN = 8.192 MHz
AD2S1210
Parameter
Tracking Rate
10-bit
Min
Typ
12-bit
14-bit
16-bit
Acceleration Error
10-bit
12-bit
14-bit
16-bit
Settling Time 10° Step Input
10-bit
12-bit
14-bit
16-bit
Settling Time 179° Step Input
10-bit
12-bit
14-bit
16-bit
EXC, EXC OUTPUTS
Voltage
Max
Unit
Conditions/Comments
3125
2500
1250
1000
625
500
156.25
125
rps
CLKIN = 10.24 MHz
CLKIN = 8.192 MHz
CLKIN = 10.24 MHz
CLKIN = 8.192 MHz
CLKIN = 10.24 MHz
CLKIN = 8.192 MHz
CLKIN = 10.24 MHz
CLKIN = 8.192 MHz
30
30
30
30
rps
rps
rps
arc min
arc min
arc min
arc min
At 50,000 rps2, CLKIN = 8.192 MHz
At 10,000 rps2, CLKIN = 8.192 MHz
At 2500 rps2, CLKIN = 8.192 MHz
At 125 rps2, CLKIN = 8.192 MHz
0.6
2.2
6.5
27.5
0.9
3.1
9.0
40
ms
ms
ms
ms
To settle to within ±2 LSB , CLKIN = 8.192 MHz
To settle to within ±2 LSB, CLKIN = 8.192 MHz
To settle to within ±2 LSB , CLKIN = 8.192 MHz
To settle to within ±2 LSB, CLKIN = 8.192 MHz
1.5
4.75
10.5
45
2.2
6.0
14.7
66
ms
ms
ms
ms
To settle to within ±2 LSB , CLKIN = 8.192 MHz
To settle to within ±2 LSB, CLKIN = 8.192 MHz
To settle to within ±2 LSB , CLKIN = 8.192 MHz
To settle to within ±2 LSB, CLKIN = 8.192 MHz
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Center Voltage
Frequency
EXC/EXC DC Mismatch
EXC/EXC AC Mismatch
THD
VOLTAGE REFERENCE
REFOUT
Drift
PSRR
CLKIN, XTALOUT6
VIL Voltage Input Low
VIH Voltage Input High
LOGIC INPUTS
VIL Voltage Input Low
VIH Voltage Input High
3.2
3.6
4.0
V p-p
2.40
2
2.47
2.53
20
30
100
V
kHz
mV
mV
dB
−58
2.40
IOZH High Level Three-State Leakage
IOZL Low Level Three-State Leakage
First five harmonics
2.53
V
ppm/°C
dB
0.8
V
V
0.8
0.7
V
V
V
V
μA
VDRIVE = 2.7 V to 5.25 V
VDRIVE = 2.3 V to 2.7 V
VDRIVE = 2.7 V to 5.25 V
VDRIVE = 2.3 V to 2.7 V
μA
RES0, RES1, RD, WR/FSYNC, A0, A1, and RESET pins
2.0
2.0
1.7
IIL Low Level Input Current (Non
Pull-Up)
IIL Low Level Input Current (Pull-Up)
IIH High Level Input Current
LOGIC OUTPUTS
VOL Voltage Output Low
VOH Voltage Output High
2.47
100
−60
Load ±100 μA, typical differential output
(EXC to EXC) = 7.2 V p-p
10
80
−10
±IOUT = 100 μA
μA
0.4
2.4
2.0
−10
10
Rev. 0 | Page 4 of 36
V
V
V
μA
μA
VDRIVE = 2.3 V to 5.25 V
VDRIVE = 2.7 V to 5.25 V
VDRIVE = 2.3 V to 2.7 V
AD2S1210
Parameter
POWER REQUIREMENTS
AVDD
DVDD
VDRIVE
POWER SUPPLY
IAVDD
IDVDD
IOVDD
Min
4.75
4.75
2.3
Typ
Max
Unit
5.25
5.25
5.25
V
V
V
12
35
2
mA
mA
mA
Conditions/Comments
1
Temperature ranges are as follows: A, B grades: –40°C to +85°C; C, D grades: –40°C to +125°C.
The voltages, SIN, SINLO, COS, and COSLO, relative to AGND, must always be between 0.15 V and AVDD − 0.2 V.
All specifications within the angular accuracy parameter are tested at constant velocity, that is, zero acceleration.
4
The velocity accuracy specification includes velocity offset and dynamic ripple.
5
For example when RES0 = 0 and RES1 = 1, the position output has a resolution of 12 bits. The velocity output has a resolution of 11 bits with the MSB indicating the
direction of rotation. In this example, with a CLKIN frequency of 8.192 MHz the velocity LSB is 0.488 rps, that is, 1000 rps/(211).
6
The clock frequency of the AD2S1210 can be supplied with a crystal, an oscillator, or directly from a DSP/microprocessor digital output. When using a single-ended
clock signal directly from the DSP/microprocessor, the XTALOUT pin should remain open circuit and the logic levels outlined under the logic inputs parameter in Table 1 apply.
2
3
www.BDTIC.com/ADI
Rev. 0 | Page 5 of 36
AD2S1210
TIMING SPECIFICATIONS
AVDD = DVDD = 5.0 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.1
Table 2.
Parameter
fCLKIN
Description
Frequency of clock input
tCK
Clock period ( = 1/fCLKIN)
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
A0 and A1 setup time before RD/CS low
Delay CS falling edge to WR/FSYNC rising edge
Address/data setup time during a write cycle
Address/data hold time during a write cycle
Delay WR/FSYNC rising edge to CS rising edge
Delay CS rising edge to CS falling edge
Delay between writing address and writing data
A0 and A1 hold time after WR/FSYNC rising edge
Delay between successive write cycles
Delay between rising edge of WR/FSYNC and falling edge of RD
Delay CS falling edge to RD falling edge
Enable delay RD low to data valid in configuration mode
VDRIVE = 4.5 V to 5.25 V
VDRIVE = 2.7 V to 3.6 V
VDRIVE = 2.3 V to 2.7 V
RD rising edge to CS rising edge
Disable delay RD high to data high-Z
Disable delay CS high to data high-Z
Delay between rising edge of RD and falling edge of WR/FSYNC
SAMPLE pulse width
Delay from SAMPLE before RD/CS low
Hold time RD before RD low
Enable delay RD/CS low to data valid
VDRIVE = 4.5 V to 5.25 V
VDRIVE = 2.7 V to 3.6 V
VDRIVE = 2.3 V to 2.7 V
RD pulse width
A0 and A1 set time to data valid when RD/CS low
VDRIVE = 4.5 V to 5.25 V
VDRIVE = 2.7 V to 3.6 V
VDRIVE = 2.3 V to 2.7 V
Delay WR/FSYNC falling edge to SCLK rising edge
Delay WR/FSYNC falling edge to SDO release from high-Z
VDRIVE = 4.5 V to 5.25 V
VDRIVE = 2.7 V to 3.6 V
VDRIVE = 2.3 V to 2.7 V
Delay SCLK rising edge to DBx valid
VDRIVE = 4.5 V to 5.25 V
VDRIVE = 2.7 V to 3.6 V
VDRIVE = 2.3 V to 2.7 V
SCLK high time
SCLK low time
SDI setup time prior to SCLK falling edge
SDI hold time after SCLK falling edge
t13
t14A
t14B
t15
t16
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
Limit at TMIN, TMAX
6.144
10.24
98
163
2
22
3
2
2
10
2 × tCK + 20
2
6 × tCK + 20
2
2
Unit
MHz min
MHz max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
37
25
30
2
16
16
2
2 × tCK + 20
6 × tCK + 20
2
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
17
21
33
6
ns min
ns min
ns min
ns min
36
37
29
3
ns min
ns min
ns min
ns min
16
26
29
ns min
ns min
ns min
24
18
32
0.4 × tCK
0.4 × tCK
3
2
ns min
ns min
ns min
ns min
ns min
ns min
ns min
www.BDTIC.com/ADI
Rev. 0 | Page 6 of 36
AD2S1210
Parameter
t29
t30
t31
t32
t33
t34
fSCLK
1
2
Description
Delay WR/FSYNC rising edge to SDO high-Z
Delay from SAMPLE before WR/FSYNC falling edge
Delay CS falling edge to WR/FSYNC falling edge in normal mode
A0 and A1 setup time before WR/FSYNC falling edge
A0 and A1 hold time after WR/FSYNC falling edge2
In normal mode, A0 = 0, A1 = 0/1
In configuration mode, A0 = 1, A1 = 1
Delay WR/FSYNC rising edge to WR/FSYNC falling edge
Frequency of SCLK input
VDRIVE = 4.5 V to 5.25 V
VDRIVE = 2.7 V to 3.6 V
VDRIVE = 2.3 V to 2.7 V
Limit at TMIN, TMAX
15
6 × tCK + 20 ns
2
2
Unit
ns min
ns min
ns min
ns min
24 × tCK + 5 ns
8 × tCK + 5 ns
10
ns min
ns min
ns min
20
25
15
MHz
MHz
MHz
Temperature ranges are as follows: A, B grades: –40°C to +85°C; C, D grades: –40°C to +125°C.
A0 and A1 should remain constant for the duration of the serial readback. This may require 24 clock periods to read back the 8-bit fault information in addition to the
16 bits of position/velocity data. If the fault information is not required, A0/A1 may be released following 16 clock cycles.
www.BDTIC.com/ADI
Rev. 0 | Page 7 of 36
AD2S1210
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
AVDD to AGND, DGND
DVDD to AGND, DGND
VDRIVE to AGND, DGND
AVDD to DVDD
AGND to DGND
Analog Input Voltage to AGND
Digital Input Voltage to DGND
Digital Output Voltage to DGND
Analog Output Voltage Swing
Input Current to Any Pin Except Supplies1
Operating Temperature Range (Ambient)
A, B Grades
C, D Grades
Storage Temperature Range
θJA Thermal Impedance2
θJA Thermal Impedance2
RoHS-Compliant Temperature, Soldering
Reflow
ESD
1
2
Rating
−0.3 V to +7.0 V
−0.3 V to +7.0 V
−0.3 V to AVDD
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to AVDD + 0.3 V
±10 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
−40°C to +85°C
−40°C to +125°C
−65°C to +150°C
54°C/W
15°C/W
260(−5/+0)oC
2 kV HBM
Transient currents of up to 100 mA do not cause latch-up.
JEDEC 2S2P standard board.
www.BDTIC.com/ADI
Rev. 0 | Page 8 of 36
AD2S1210
A0
EXC
EXC
AGND
SIN
SINLO
COSLO
AVDD
COS
REFBYP
REFOUT
RES0
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
RES1 1
36 A1
PIN 1
CS 2
35 DOS
34 LOT
RD 3
WR/FSYNC 4
33 RESET
DGND 5
32 DIR
AD2S1210
DVDD 6
31 NM
TOP VIEW
(Not to Scale)
CLKIN 7
30 B
XTALOUT 8
29 A
SOE 9
28 DB0
SAMPLE 10
27 DB1
DB15/SDO 11
26 DB2
DB14/SDI 12
25 DB3
07467-002
DB4
DB5
DB6
DB7
DB8
DGND
VDRIVE
DB9
DB10
DB11
DB12
DB13/SCLK
13 14 15 16 17 18 19 20 21 22 23 24
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin
No.
1
Mnemonic
RES1
2
3
CS
RD
4
WR/FSYNC
5, 19
DGND
6
DVDD
7
CLKIN
8
XTALOUT
9
SOE
10
SAMPLE
11
DB15/SDO
12
DB14/SDI
Description
Resolution Select 1. Logic input. RES1 in conjunction with RES0 allows the resolution of the AD2S1210 to be
programmed. Refer to the Configuration of AD2S1210 section.
Chip Select. Active low logic input. The device is enabled when CS is held low.
Edge-Triggered Logic Input. When the SOE pin is high, this pin acts as a frame synchronization signal and output
enable for the parallel data outputs, DB15 to DB0. The output buffer is enabled when CS and RD are held low. When
the SOE pin is low, the RD pin should be held high.
Edge-Triggered Logic Input. When the SOE pin is high, this pin acts as a frame synchronization signal and input
enable for the parallel data inputs, DB7 to DB0. The input buffer is enabled when CS and WR/FSYNC are held low.
When the SOE pin is low, the WR/FSYNC pin acts as a frame synchronization signal and enable for the serial data bus.
Digital Ground. These pins are ground reference points for digital circuitry on the AD2S1210. Refer all digital input
signals to this DGND voltage. Both of these pins can be connected to the AGND plane of a system. The DGND and
AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.
Digital Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for all digital circuitry on the AD2S1210. The AVDD and DVDD
voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis.
Clock Input. A crystal or oscillator can be used at the CLKIN and XTALOUT pins to supply the required clock frequency of
the AD2S1210. Alternatively, a single-ended clock can be applied to the CLKIN pin. The input frequency of the AD2S1210 is
specified from 6.144 MHz to 10.24 MHz.
Crystal Output. When using a crystal or oscillator to supply the clock frequency to the AD2S1210, apply the crystal
across the CLKIN and XTALOUT pins. When using a single-ended clock source, the XTALOUT pin should be
considered a no connect pin.
Serial Output Enable. Logic input. This pin enables either the parallel or serial interface. The serial interface is selected
by holding the SOE pin low, and the parallel interface is selected by holding the SOE pin high.
Sample Result. Logic input. Data is transferred from the position and velocity integrators to the position and velocity
registers, after a high-to-low transition on the SAMPLE signal. The fault register is also updated after a high-to-low
transition on the SAMPLE signal.
Data Bit 15/Serial Data Output Bus. When the SOE pin is high, this pin acts as DB15, a three-state data output pin
controlled by CS and RD. When the SOE pin is low, this pin acts as SDO, the serial data output bus controlled by CS and
WR/FSYNC. The bits are clocked out on the rising edge of SCLK.
Data Bit 14/Serial Data Input Bus. When the SOE pin is high, this pin acts as DB14, a three-state data output pin controlled
by CS and RD. When the SOE pin is low, this pin acts as SDI, the serial data input bus controlled by CS and WR/FSYNC. The
bits are clocked in on the falling edge of SCLK.
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Rev. 0 | Page 9 of 36
AD2S1210
Pin
No.
13
Mnemonic
DB13/SCLK
14 to
17
18
DB12 to
DB9
VDRIVE
20
21 to
28
29
DB8
DB7 to DB0
30
B
31
NM
32
DIR
33
RESET
34
LOT
35
DOS
36
A1
37
A0
38
EXC
39
EXC
40
AGND
41
42
43
SIN
SINLO
AVDD
44
45
46
47
48
COSLO
COS
REFBYP
REFOUT
RES0
A
Description
Data Bit 13/Serial Clock. In parallel mode, this pin acts as DB13, a three-state data output pin controlled by CS and RD. In
serial mode, this pin acts as the serial clock input.
Data Bit 12 to Data Bit 9. Three-state data output pins controlled by CS and RD.
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates.
Decouple this pin to DGND. The voltage range on this pin is 2.3 V to 5.25 V and may be different to the voltage range
at AVDD and DVDD but should never exceed either by more than 0.3 V.
Data Bit 8. Three-state data output pin controlled by CS and RD.
Data Bit 7 to Data Bit 0. Three-state data input/output pins controlled by CS, RD, and WR/FSYNC.
Incremental Encoder Emulation Output A. Logic output. This output is free running and is valid if the resolver format
input signals applied to the converter are valid.
Incremental Encoder Emulation Output B. Logic output. This output is free running and is valid if the resolver format
input signals applied to the converter are valid.
North Marker Incremental Encoder Emulation Output. Logic output. This output is free running and is valid if the
resolver format input signals applied to the converter are valid.
Direction. Logic output. This output is used in conjunction with the incremental encoder emulation outputs. The DIR
output indicates the direction of the input rotation and is high for increasing angular rotation.
Reset. Logic input. The AD2S1210 requires an external reset signal to hold the RESET input low until VDD is within the
specified operating range of 4.75 V to 5.25 V.
Loss of Tracking. Logic output. LOT is indicated by a logic low on the LOT pin and is not latched. Refer to the Loss of
Position Tracking Detection section.
Degradation of Signal. Logic output. Degradation of signal (DOS) is detected when either resolver input (sine or cosine)
exceeds the specified DOS sine/cosine threshold or when an amplitude mismatch occurs between the sine and
cosine input voltages. DOS is indicated by a logic low on the DOS pin. Refer to the Signal Degradation Detection
section.
Mode Select 1. Logic input. A1 in conjunction with A0 allows the mode of the AD2S1210 to be selected. Refer to the
Configuration of AD2S1210 section.
Mode Select 0. Logic input. A0 in conjunction with A1 allows the mode of the AD2S1210 to be selected. Refer to the
Configuration of AD2S1210 section.
Excitation Frequency. Analog output. An on-board oscillator provides the sinusoidal excitation signal (EXC) and its
complement signal (EXC) to the resolver. The frequency of this reference signal is programmable via the excitation
frequency register.
Excitation Frequency Complement. Analog output. An on-board oscillator provides the sinusoidal excitation signal
(EXC) and its complement signal (EXC) to the resolver. The frequency of this reference signal is programmable via the
excitation frequency register.
Analog Ground. This pin is the ground reference points for analog circuitry on the AD2S1210. Refer all analog input
signals and any external reference signal to this AGND voltage. Connect the AGND pin to the AGND plane of a
system. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V
apart, even on a transient basis.
Positive Analog Input of Differential SIN/SINLO Pair. The input range is 2.3 V p-p to 4.0 V p-p.
Negative Analog Input of Differential SIN/SINLO Pair. The input range is 2.3 V p-p to 4.0 V p-p.
Analog Supply Voltage, 4.75 V to 5.25 V. This pin is the supply voltage for all analog circuitry on the AD2S1210. The
AVDD and DVDD voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a
transient basis.
Negative Analog Input of Differential COS/COSLO Pair. The input range is 2.3 V p-p to 4.0 V p-p.
Positive Analog Input of Differential COS/COSLO Pair. The input range is 2.3 V p-p to 4.0 V p-p.
Reference Bypass. Connect reference decoupling capacitors at this pin. Typical recommended values are 10 μF and 0.01 μF.
Voltage Reference Output.
Resolution Select 0. Logic input. RES0 in conjunction with RES1 allows the resolution of the AD2S1210 to be
programmed. Refer to the Configuration of AD2S1210 section.
www.BDTIC.com/ADI
Rev. 0 | Page 10 of 36
AD2S1210
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, AVDD = DVDD = VDRIVE = 5 V, SIN/SINLO = 3.15 V p-p, COS/COSLO = 3.15 V p-p, CLKIN = 8.192 MHz , unless otherwise noted.
400
200
180
350
160
300
HITS PER CODE
HITS PER CODE
140
250
200
150
120
100
80
60
100
07467-003
CODE
8178
8179
8180
8181
8182
8183
8184
8185
8186
8187
8188
8189
8190
8191
8192
8193
8194
8195
8196
8197
8198
8199
8200
8201
8202
8203
8204
8205
8206
0
8178
8179
8180
8181
8182
8183
8184
8185
8186
8187
8188
8189
8190
8191
8192
8193
8194
8195
8196
8197
8198
8199
8200
8201
8202
8203
8204
8205
8206
20
0
CODE
Figure 3. Typical 16-Bit Angular Accuracy Histogram Of Codes, 512 Samples
07467-006
40
50
Figure 6. Typical 12-Bit Angular Accuracy Histogram of Codes, 512 Samples,
Hysteresis Disabled
600
500
450
500
400
300
250
200
www.BDTIC.com/ADI
HITS PER CODE
HITS PER CODE
350
150
100
400
300
200
100
0
CODE
07467-004
8178
8179
8180
8181
8182
8183
8184
8185
8186
8187
8188
8189
8190
8191
8192
8193
8194
8195
8196
8197
8198
8199
8200
8201
8202
8203
8204
8205
8206
0
Figure 4. Typical 14-Bit Angular Accuracy Histogram of Codes, 512 Samples,
Hysteresis Disabled
510
511
512
CODES
513
514
07467-017
50
Figure 7. Typical 12-Bit Angular Accuracy Histogram of Codes, 512 Samples,
Hysteresis Enabled
60
600
50
HITS PER CODE
HITS PER CODE
500
400
300
40
30
20
200
10
100
2047
CODES
2048
2049
CODE
Figure 5. Typical 14-Bit Angular Accuracy Histogram of Codes, 512 Samples,
Hysteresis Enabled
07467-018
2046
07467-005
2045
8178
8179
8180
8181
8182
8183
8184
8185
8186
8187
8188
8189
8190
8191
8192
8193
8194
8195
8196
8197
8198
8199
8200
8201
8202
8203
8204
8205
8206
0
0
Figure 8. Typical 10-Bit Angular Accuracy Histogram of Codes, 512 Samples,
Hysteresis Disabled
Rev. 0 | Page 11 of 36
AD2S1210
20
600
18
16
14
400
ANGLE (Degrees)
HITS PER CODE
500
300
200
12
10
8
6
4
100
127
128
CODES
129
0
07467-038
126
130
0
20
18
18
16
16
14
14
ANGLE (Degrees)
20
12
10
8
4
4.00
4.50
5.00
12
10
8
6
4
8
12
16
20
24
TIME (ms)
28
32
36
40
0
0
225
16
200
14
175
ANGLE (Degrees)
250
18
12
10
8
6
7
8
9
10
0
07467-009
5
6
TIME (ms)
2.00
2.25
2.50
72
80
75
25
4
1.75
100
2
3
1.00 1.25 1.50
TIME (ms)
125
50
2
0.75
150
4
1
0.50
Figure 13. Typical 10-Bit 10° Step Response
20
0
0.25
Figure 11. Typical 14-Bit 10° Step Response
0
8
16
24
32
40
48
TIME (ms)
56
64
Figure 14. Typical 16-Bit 179° Step Response
Rev. 0 | Page 12 of 36
07467-014
0
07467-007
2
Figure 10. Typical 16-Bit 10° Step Response
ANGLE (Degrees)
3.50
4
2
0
1.50 2.00 2.50 3.00
TIME (ms)
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6
0
1.00
Figure 12. Typical 12-Bit 10° Step Response
07467-010
ANGLE (Degrees)
Figure 9. Typical 10-Bit Angular Accuracy Histogram of Codes, 512 Samples,
Hysteresis Enabled
0.50
07467-008
2
0
250
5
225
0
–5
175
–10
150
125
100
75
–25
–40
4
6
8
10
12
TIME (ms)
14
16
18
20
16-BIT
–30
25
2
–45
1
10
0
225
–20
200
–40
175
–60
150
–80
PHASE (dB)
125
100
100k
14-BIT
12-BIT
–100
–120
16-BIT
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75
–140
–160
25
0
1
2
3
4
5
6
TIME (ms)
7
8
9
10
–200
1
10
100
1k
FREQUENCY (Hz)
10k
100k
Figure 19. Typical System Phase Response
10
225
9
200
8
TRACKING ERROR (Degrees)
250
175
150
125
100
75
50
25
7
6
5
4
3
2
1
2
3
4
TIME (ms)
5
0
Figure 17. Typical 10-Bit 179° Step Response
0
500
1000
1500
ACCELERATION (rps2)
2000
2500
Figure 20. Typical 16-Bit Tracking Error vs. Acceleration
Rev. 0 | Page 13 of 36
07467-022
0
07467-011
1
07467-016
–180
Figure 16. Typical 12-Bit 179° Step Response
ANGLE (Degrees)
10k
10-BIT
07467-012
ANGLE (Degrees)
250
50
0
100
1k
FREQUENCY (Hz)
Figure 18. Typical System Magnitude Response
Figure 15. Typical 14-Bit 179° Step Response
0
12-BIT
–20
–35
0
14-BIT
–15
50
0
10-BIT
07467-015
MAGNITUDE (dB)
200
07467-013
ANGLE (Degrees)
AD2S1210
10
10
9
9
8
8
TRACKING ERROR (Degrees)
7
6
5
4
3
2
0
6
5
4
3
2
1
0
5000 10000 15000 20000 25000 30000 35000 40000 45000
ACCELERATION (rps2)
07467-021
1
7
0
Figure 21. Typical 14-Bit Tracking Error vs. Acceleration
0
200000
400000
600000
800000
ACCELERATION (rps2)
1000000
07467-019
TRACKING ERROR (Degrees)
AD2S1210
Figure 23. Typical 10-Bit Tracking Error vs. Acceleration
10
8
7
6
5
4
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3
2
1
0
0
20000
60000
100000
ACCELERATION (rps2)
140000
180000
07467-020
TRACKING ERROR (Degrees)
9
Figure 22. Typical 12-Bit Tracking Error vs. Acceleration
Rev. 0 | Page 14 of 36
AD2S1210
RESOLVER FORMAT SIGNALS
Vr = Vp × sin(ωt)
Vr = Vp × sin(ωt)
R1
S2
S2
Va = Vs × sin(ωt) × cos(θ)
θ
R1
Va = Vs × sin(ωt) × cos(θ)
θ
S4
S4
R2
R2
S3
S1
Vb = Vs × sin(ωt) × sin(θ)
S3
Vb = Vs × sin(ωt) × sin(θ)
(A) CLASSICAL RESOLVER
07467-023
S1
(B) VARIABLE RELUCTANCE RESOLVER
Figure 24. Classical Resolver vs. Variable Reluctance Resolver
A resolver is a rotating transformer, typically with a primary
winding on the rotor and two secondary windings on the stator.
In the case of a variable reluctance resolver, there are no windings on the rotor, as shown in Figure 24. The primary winding
is on the stator as well as the secondary windings, but the saliency
in the rotor design provides the sinusoidal variation in the
secondary coupling with the angular position. Either way, the
resolver output voltages (S3 − S1, S2 − S4) have the same
equations, as shown in Equation 1.
S3 − S1 = E 0 sin ωt × sin θ
The stator windings are displaced mechanically by 90° (see
Figure 24). The primary winding is excited with an ac reference.
The amplitude of subsequent coupling onto the stator secondary
windings is a function of the position of the rotor (shaft) relative to
the stator. The resolver, therefore, produces two output voltages
(S3 − S1, S2 − S4) modulated by the sine and cosine of shaft
angle. Resolver format signals refer to the signals derived from
the output of a resolver, as shown in Equation 1. Figure 25
illustrates the output format.
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where:
θ is the shaft angle.
Sinωt is the rotor excitation frequency.
E0 is the rotor excitation amplitude.
(1)
S2 – S4
(cos)
S3 – S1
(sin)
R2 – R4
(REF)
0°
90°
180°
270°
θ
Figure 25. Electrical Resolver Representation
Rev. 0 | Page 15 of 36
360°
07467-024
S2 − S 4 = E 0 sin ωt × cos θ
AD2S1210
THEORY OF OPERATION
Monitor = A1 × sin θ × sin φ + A2 × cos θ × cos φ
RESOLVER TO DIGITAL CONVERSION
The AD2S1210 operates on a Type II tracking closed-loop
principle. The output continually tracks the position of the
resolver without the need for external conversion and wait
states. As the resolver moves through a position equivalent
to the least significant bit weighting, the output is updated by
one LSB.
(4)
where:
A1 is the amplitude of the incoming sine signal (A1 × sinθ).
A2 is the amplitude of the incoming cosine signal (A2 × cosθ).
θ is the resolver angle.
ϕ is the angle stored in the position register.
The converter tracks the shaft angle θ by producing an output
angle ϕ that is fed back and compared to the input angle θ, and
the resulting error between the two is driven towards 0 when
the converter is correctly tracking the input angle. To measure
the error, S3 − S1 is multiplied by cosϕ and S2 − S4 is multiplied by
sinϕ to give
E 0 sin ωt × sin θ cos φ (for S3 − S1)
E 0 sin ωt × cos θ sin φ (for S2 − S4)
The difference is taken, giving
Note that Equation 4 is shown after demodulation, with the
Carrier Signal sinωt removed. Also, note that for matched input
signal (that is, a no fault condition), A1 = A2.
When A1 = A2 and the converter is tracking (θ = ϕ), the
monitor signal output has a constant magnitude of A1 (Monitor
= A1 × (sin2 θ + cos2 θ) = A1), which is independent of shaft
angle. When A1 ≠ A2, the monitor signal magnitude varies
between A1 and A2 at twice the rate of shaft rotation. The
monitor signal is used as described in the following sections to
detect degradation or loss of input signals.
Loss of Signal Detection
E 0 sin ωt × (sin θ cos φ − cos θ sin φ )
(2)
This signal is demodulated using the internally generated
synthetic reference, yielding
The AD2S1210 indicates that a loss of signal (LOS) has
occurred for four separate conditions.
•
E 0 (sin θ cos φ − cos θ sin φ )
When either resolver input (sine or cosine) falls below the
specified LOS sine/cosine threshold. This threshold is
defined by the user and is set by writing to the internal
register, Address 0x88 (see the Register Map section).
When any of the resolver input pins (SIN, SINLO, COS, or
COSLO) are disconnected from the sensor.
When any of the resolver input pins (SIN, SINLO, COS, or
COSLO) are clipping the power rail or ground rail of the
AD2S1210. Refer to the Sine/Cosine Input Clipping section.
When a configuration parity error has occurred. Refer to
the Configuration Parity Error section.
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(3)
Equation 3 is equivalent to E0sin(θ − ϕ), which is approximately
equal to E0(θ − ϕ) for small values of θ − ϕ, where θ − ϕ =
angular error.
The value E0 (θ − ϕ) is the difference between the angular error
of the rotor and the digital angle output of the converter.
A phase-sensitive demodulator, some integrators, and a compensation filter form a closed-loop system that seeks to null the error
signal. When this is accomplished, ϕ equals the Resolver Angle θ
within the rated accuracy of the converter. A Type II tracking
loop is used so that constant velocity inputs can be tracked
without inherent error.
FAULT DETECTION CIRCUIT
The AD2S1210 fault detection circuit can sense loss of resolver
signals, out-of-range input signals, input signal mismatch, or
loss of position tracking; however, in the event of a fault, the
position indicated by the AD2S1210 may differ significantly
from the actual shaft position of the resolver.
Monitor Signal
The AD2S1210 generates a monitor signal by comparing the
angle in the position register to the incoming sine and cosine
signals from the resolver. The monitor signal is created in a
similar fashion to the error signal described in the Resolver to
Digital Conversion section. The incoming signals, sinθ and
cosθ, are multiplied by the sin and cos of the output angle,
respectively, and then added together.
•
•
•
A loss of signal is caused if either of the stator windings of the
resolver (sine or cosine) are open circuit or have a number of
shorted turns. LOS is indicated by both the DOS and LOT pins
latching as logic low outputs. The DOS and LOT pins are reset
to a no fault state when the user enters configuration mode and
reads the fault register. The LOS condition has priority over
both the DOS and LOT conditions, as shown in Table 6. To
determine the cause of the LOS fault detection, the user must
read the fault register, Address 0xFF (see the Register Map
section).
When a loss of signal is detected due to the resolver inputs (sine
or cosine) falling below the specified LOS sine/cosine threshold,
the electrical angle through which the resolver may rotate before
the LOS can be detected by the AD2S1210 is referred to as the
LOS angular latency. This is defined by the specified LOS sine/
cosine threshold set by the user and the maximum amplitude of
the input signals being applied to the AD2S1210. The worst-case
angular latency can be calculated as follows:
Rev. 0 | Page 16 of 36
AD2S1210
Angular Latency =
⎡
⎤
LOS threshold
2 × Arc cos ⎢
⎥
⎢⎣ max sine / cosine amplitude ⎥⎦
window counter periods for the range of excitation frequencies
on the AD2S1210 are outlined in Table 5.
(5)
The preceding equation is based on the worst-case angular
error, which can be seen by the AD2S1210 before an LOS fault
is indicated. This occurs if one of the resolver input signals,
either sine or cosine, is lost while the remaining signal is at its
peak amplitude, for example, if the sine input is lost while the
input angle is 90°. The worst-case angular latency is twice the
worst-case angular error.
The AD2S1210 indicates that a degradation of signal (DOS) has
occurred for two separate conditions.
•
Excitation Frequency
Range
2 kHz ≤ Exc Freq < 4 kHz
4 kHz ≤ Exc Freq < 8 kHz
8 kHz ≤ Exc Freq ≤ 20 kHz
1
Signal Degradation Detection
•
Table 5. Window Counter Period vs. Excitation Frequency
Range, CLKIN = 8.192 MHz
When either resolver input (sine or cosine) exceeds the
specified DOS sine/cosine threshold. This threshold is
defined by the user and is set by writing to the internal
register, Address 0x89 (see the Register Map section).
When the amplitudes of the input signals, sine and cosine,
mismatch by more than the specified DOS sine/cosine
mismatch threshold. This threshold is defined by the user
and is set by writing to the internal register, Address 0x8A
(see the Register Map section). The AD2S1210 continuously
stores the minimum and maximum magnitude of the monitor signal in internal registers. The difference between the
minimum and maximum is calculated to determine if a
DOS mismatch has occurred. The initial values for the
minimum and maximum internal registers must be defined
by the user, at Address 0x8C and Address 0x8B, respectively
(see the Register Map section).
Number of
Internal Clock
Cycles
1065
554
256
Window
Counter Period
(μs)1
260
135.25
62.5
CLKIN = 8.192 MHz. The window counter period scales with clock frequency
and can be calculated by multiplying the number of internal clock cycles by
the period of the internal clock frequency, that is, CLKIN/2.
The AD2S1210 detects an LOS or DOS due to the resolver inputs
(sine or cosine) falling below or exceeding the LOS and DOS
thresholds within two window counter periods. For example,
with an excitation frequency of 10 kHz, a fault is detected within
125 μs. A persistent fault is detected within one window counter
period of the reading and clearing the fault register.
Note that the time latency to detect the occurrence of a DOS
mismatch fault is dependent on the speed of rotation of the
resolver. The worst-case time latency to detect a DOS mismatch
fault is the time required for one full rotation of the resolver.
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DOS is indicated by a logic low on the DOS pin. When DOS is
indicated, the output is latched low until the user enters configuration mode and reads the fault register. The DOS condition has
priority over the LOT condition, as shown in Table 6. To determine the cause of the DOS fault detection, the user must read
the fault register, Address 0xFF (see the Register Map section).
Time Latency for LOS and DOS Detection
Note that the monitor signal is generated on the active edge of
the internal AD2S1210 clock. The internal clock is generated
by dividing the externally applied CLKIN frequency by 2; for
example, when using a CLKIN frequency of 8.192 MHz the
internal AD2S1210 clock is 4.096 MHz. The AD2S1210 continuously stores the minimum and maximum magnitude of the
monitor signal in internal registers. The values stored in these
internal registers are compared to the LOS and DOS thresholds
configured by the user at set intervals. This interval, known as
the window counter period, is dependent on the excitation
frequency configured by the user. It is set to ensure that two
window counter periods include at least one full period of the
excitation frequency applied to the resolver. The window
counter period is defined in terms of internal clock cycles. The
Loss of Position Tracking Detection
The AD2S1210 indicates that a loss of tracking (LOT) has
occurred when
•
•
The internal error signal of the AD2S1210 has exceeded
the specified angular threshold. This threshold is defined
by the user and is set by writing to the internal register,
Address 0x8D (see the Register Map section).
The input signal exceeds the maximum tracking rate. The
maximum tracking rate depends on the resolution defined
by the user and the CLKIN frequency.
LOT is indicated by a logic low on the LOT pin and is not latched.
LOT has hysteresis and is not cleared until the internal error
signal is less than the value defined in the LOT low threshold
register, Address 0x8E (see the Register Map section).
When the maximum tracking rate is exceeded, LOT is cleared
only if the velocity is less than the maximum tracking rate and
the internal error signal is less than the value defined in the LOT
low threshold register. LOT can be indicated for step changes in
position (such as after a RESET signal is applied to the AD2S1210).
It is also useful as a built-in test to indicate that the tracking
converter is functioning properly. The LOT condition has lower
priority than both the DOS and LOS conditions, as shown in
Table 6. The LOT and DOS conditions cannot be indicated using
the LOT and DOS pins at the same time. However, both conditions are indicated separately in the fault register. To determine
the cause of the LOT fault detection, the user must read the fault
register, Address 0xFF (see the Register Map section).
Rev. 0 | Page 17 of 36
AD2S1210
Table 6. Fault Detection Decoding
Condition
Loss of Signal (LOS)
Degradation of Signal (DOS)
Loss of Tracking (LOT)
No Fault
DOS Pin
0
0
1
1
LOT Pin
0
1
0
1
Order of
Priority
1
2
3
N/A
The AD2S1210 also provides an internal synthetic reference
signal that is phase locked to its sine and cosine inputs. Phase
errors between the resolver primary and secondary windings
can degrade the accuracy of the RDC and are compensated by
this synchronous reference signal. This also compensates the
phase shifts due to temperature and cabling and eliminates the
need of an external preset phase compensation circuit.
Sine/Cosine Input Clipping
SYNTHETIC REFERENCE GENERATION
The AD2S1210 indicates that a clipping error has occurred if
any of the resolver input pins (SIN, SINLO, COS, or COSLO)
are clipping the power rail or ground rail of the AD2S1210. The
clipping fault is indicated if the input amplitudes are less than
0.15 V or greater then AVDD − 0.2 V for more than 4 μs.
When a resolver undergoes a high rotation rate, the RDC tends
to act as an electric motor and produces speed voltages, along
with the ideal sine and cosine outputs. These speed voltages are
in quadrature to the main signal waveform. Moreover, nonzero
resistance in the resolver windings causes a nonzero phase shift
between the reference input and the sine and cosine outputs.
The combination of speed voltages and phase shift causes a tracking error in the RDC that is approximated by
Sine/cosine input clipping error is indicated by both the DOS and
LOT pins latching as logic low outputs. Sine/cosine input clipping
error is also indicated by Bit D7 of the fault register being set high.
The DOS and LOT pins are reset to a no fault state when the
user enters configuration mode and reads the fault register.
Configuration Parity Error
The AD2S1210 includes a number of user programmable registers
that allow the user to configure the part. Each read/write register
on the AD2S1210 is programmed with seven bits of information by the user. The 8th bit is reserved as a parity error bit. In
the event that the data within these registers becomes corrupted,
the AD2S1210 indicates that a configuration parity error has
occurred. Configuration parity error is indicated by both the DOS
and LOT pins latching as logic low outputs. Configuration parity
error is also indicated by Bit D0 of the fault register being set
high. In the event that a parity error occurs, it is recommended
that the user reset the part using the RESET pin.
Error = Phase Shift ×
Rotation Rate
Reference Frequency
(6)
To compensate for the described phase error between the resolver
reference excitation and the sine/cosine signals, an internal
synthetic reference signal is generated in phase with the reference frequency carrier. The synthetic reference is derived using
the internally filtered sine and cosine signals. It is generated
by determining the zero crossing of either the sine or cosine
(whichever signal is larger, to improve phase accuracy) and
evaluating the phase of the resolver reference excitation. The
synthetic reference reduces the phase shift between the reference and sine/cosine inputs to less than 10°, and operates for
phase shifts of ±44°. If additional phase lock range is required,
Bit D5 in the control register can be set to zero to expand the
phase lock range to 360° (see the Control Register section).
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Phase Lock Error
The AD2S1210 indicates that a phase lock error has occurred if
the difference between the phase of the excitation frequency
and the phase of the sine and cosine signals exceeds the specified
phase lock range. Phase lock error is indicated by a logic low on
the LOT pin and is not latched. Phase lock error is also indicated
by Bit D1 of the fault register being set high.
ON-BOARD PROGRAMMABLE SINUSOIDAL
OSCILLATOR
An on-board oscillator provides the sinusoidal excitation signal
(EXC) to the resolver as well as its complemented signal (EXC).
The frequency of this reference signal is programmable to a
number of standard frequencies between 2 kHz and 20 kHz.
The amplitude of this signal is 3.6 V p-p and is centered on 2.5 V.
CONNECTING THE CONVERTER
Ground is connected to the AGND and DGND pins (see
Figure 26). A positive power supply (VDD) of 5 V dc ± 5% is
connected to the AVDD and DVDD pins, with typical values for the
decoupling capacitors being 10 nF and 4.7 μF. These capacitors
are then placed as close to the device pins as possible and are
connected to both AVDD and DVDD. The VDRIVE pin is connected
to the supply voltage of the microprocessor. The voltage applied
to the VDRIVE input controls the voltage of the parallel and serial
interfaces. VDRIVE can be set to 5 V, 3 V, or 2.5 V. Typical values
for the VDRIVE decoupling capacitors are 10 nF and 4.7 μF.
Typical values for the oscillator decoupling capacitors are 20 pF,
whereas typical values for the reference decoupling capacitors are
10 nF and 10 μF.
The reference excitation output of the AD2S1210 needs an
external buffer amplifier to provide gain and the additional
current to drive a resolver.
Rev. 0 | Page 18 of 36
AD2S1210
S2
S4
5V
S1
R1
BUFFER
CIRCUIT
2
EXC
EXC
SIN
AGND
SINLO
1
35
4
6
DVDD
7
CLKIN
30
8
XTALOUT
29
AD2S1210
31
9
28
10
27
11
26
12
20pF
20pF
R2 ⎞ ⎞ ⎛ R2 ⎞ ⎛
1
⎛
⎞V (8)
VOUT = ⎜ V REF × ⎛⎜1 +
⎟ IN
⎟⎟ − ⎜ ⎟×⎜
⎝ R1 ⎠ ⎠ ⎝ R1 ⎠ ⎝ 1 + R2 × C1 × ω ⎠
⎝
32
where:
ω is the radian frequency of the applied signal.
VREF, a dc voltage, is set so that VOUT is always a positive value,
eliminating the need for a negative supply.
25
C1
13 14 15 16 17 18 19 20 21 22 23 24
R2
VDRIVE
4.7µF
12V
07467-025
10nF
12V
EXC/EXC
(VIN)
Figure 26. Connecting the AD2S1210 to a Resolver
R1
(VREF ) AD8662
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In this recommended configuration, the converter introduces a
VREF/2 offset in the SIN, SINLO, COS, and COSLO signal outputs
from the resolver. The sine and cosine signals can each be
connected to a different potential relative to ground if the sine
and cosine signals adhere to the recommended specifications.
Note that because the EXC and EXC outputs are differential,
there is an inherent gain of 2×.
5V
VOUT
04767-026
8.192
MHZ
DGND
DGND
5V
(7)
and
33
5
VDRIVE
4.7µF
Carrier Gain = − (R2 / R1) × (1 /(1 + R2 × C1 × ω))
36
34
3
10nF
Figure 27 shows a suggested buffer circuit. Capacitor C1 may be
used in parallel with Resistor R2 to filter out any noise that may
exist on the EXC and EXC outputs. Care should be taken when
selecting the cutoff frequency of this filter to ensure that phase
shifts of the carrier caused by the filter do not exceed the phase
lock range of the AD2S1210.
The gain of the circuit is
48 47 46 45 44 43 42 41 40 39 38 37
COS
10µF
COSLO
AVDD
10nF
S3
BUFFER
CIRCUIT
REFBYP
10nF
REFOUT
4.7µF
R2
Figure 27. Buffer Circuit
A separate screened twisted pair cable is recommended for the
analog input pins, SIN, SINLO, COS, and COSLO. The screens
should terminate to either REFOUT or AGND.
Rev. 0 | Page 19 of 36
AD2S1210
CONFIGURATION OF AD2S1210
MODES OF OPERATION
The AD2S1210 has two modes of operation: configuration mode
and normal mode. The configuration mode is used to program
the registers that set the excitation frequency, the resolution,
and the fault detection thresholds of the AD2S1210. Configuration
mode is also used to read back the information in the fault register.
The data in the position and velocity registers can also be read
back while in configuration mode. The AD2S1210 can be operated
entirely in configuration mode or, when the initial configuration is
completed, the part can be taken out of configuration mode and
operated in normal mode. When operating in normal mode, the
data outputs can provide angular position or angular velocity
data. The A0 and A1 inputs are used to determine whether the
AD2S1210 is in configuration mode and to determine whether
the position or velocity data is supplied to the output pins, see
Table 8.
Setting the Excitation Frequency
The excitation frequency of the AD2S1210 is set by writing a
frequency control word to the excitation frequency register,
Address 0x91 (see the Register Map section).
Excitation Frequency =
(FCW × f CLKIN )
Note that the recommended frequency range for each resolution
and bandwidth, as outlined in Table 7, are defined for a clock
frequency of 8.192 MHz. The recommended excitation frequency
range scales with the clock frequency of the AD2S1210. The
default excitation frequency of the AD2S1210 is 10 kHz when
operated with a clock frequency of 8.192 MHz.
A0, A1 Inputs
The AD2S1210 allows the user to read the angular position or
the angular velocity data directly from the parallel outputs or
through the serial interface. The required information can be
selected using the A0 and A1 inputs. These inputs should also
be used to put the part into configuration mode. The data from
the fault register and the remaining on-chip registers can be
accessed in configuration mode.
Table 8. Configuration Mode Settings
A0
0
0
1
1
A1
0
1
0
1
Result
Normal mode—position output
Normal mode—velocity output
Reserved
Configuration mode
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RES0, RES1 Inputs
2 15
where FCW is the frequency control word and fCLKIN is the clock
frequency of the AD2S1210.
The specified range of the excitation frequency is from 2 kHz to
20 kHz and can be set in increments of 250 Hz. To achieve the
angular accuracy specifications in Table 1, the excitation frequency
should be selected as outlined in Table 7.
Table 7. Recommended Excitation Frequency vs. Resolution
(fCLKIN = 8.192 MHz)
Resolution
10 Bits
12 Bits
14 Bits
16 Bits
Typical
Bandwidth
4100 Hz
1700 Hz
900 Hz
250 Hz
Min Excitation
Frequency
10 kHz
6 kHz
3 kHz
2 kHz
Max Excitation
Frequency
20 kHz
20 kHz
12 kHz
10 kHz
In normal mode, the resolution of the digital output is selected
using the RES0 and RES1 input pins. In configuration mode,
the resolution is selected by setting the RES0 and RES1 bits in
the control register. When switching between normal mode and
configuration mode, it is the responsibility of the user to ensure
that the resolution set in the control register matches the resolution
set by the RES0 and RES1 input pins. Failure to do so may result
in incorrect data on the outputs, caused by the differences
between the resolution settings.
Table 9. Resolution Settings
RES0
0
0
1
1
1
RES1
0
1
0
1
Resolution
(Bits)
10
12
14
16
Position LSB
(Arc min)
21.1
5.3
1.3
0.3
Velocity LSB
(rps)1
4.88
0.488
0.03
0.004
CLKIN = 8.192 MHz. The velocity LSB size and maximum tracking rate scale
linearly with the CLKIN frequency.
Rev. 0 | Page 20 of 36
AD2S1210
REGISTER MAP
Table 10. Register Map
Register Name
Position
Velocity
LOS Threshold
DOS Overrange
Threshold
DOS Mismatch
Threshold
DOS Reset Max
Threshold
DOS Reset Min
Threshold
LOT High Threshold
LOT Low Threshold
Excitation Frequency
Control
Soft Reset
Fault
Register
Address
0x80
0x81
0x82
0x83
0x88
0x89
Register
Data
D15 to D8
D7 to D0
D15 to D8
D7 to D0
D7 to D0
D7 to D0
Read/Write
Register
Read only
Read only
Read only
Read only
Read/write
Read/write
0x8A
D7 to D0
Read/write
0x8B
D7 to D0
Read/write
0x8C
D7 to D0
Read/write
0x8D
0x8E
0x91
0x92
0xF0
0xFF
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
Read/write
Read/write
Read/write
Read/write
Write only
Read only
The value stored in the velocity register is 16 bits regardless of
resolution. At lower resolutions, the LSBs of the 16-bit digital
output should be ignored. For example, at 10-bit resolution,
Data Bit D15 to Data Bit D6 provide valid data; D5 to D0 should
be ignored. The maximum tracking rate of the AD2S1210 at
10-bit resolution with an 8.192 MHz input clock is ±2500 rps.
A velocity of +2500 rps results in 0x1FF being stored in Bit D15 to
Bit D6 of the velocity register; a velocity of −2500 rps results in
0x3FF being stored in Bit D15 to Bit D6 of the velocity register. In
this 10-bit example, the LSB size of the velocity output is 4.88 rps.
LOS THRESHOLD REGISTER
Table 13. 8-Bit Register
Address
0x88
Bit
D7 to D0
Read/Write
Read/write
The LOS threshold register determines the loss of signal threshold
of the AD2S1210. The AD2S1210 allows the user to set the LOS
threshold to a value between 0 V and 4.82 V. The resolution of
the LOS threshold is seven bits, that is, 38 mV. Note that the MSB,
D7, should be set to 0. The default value of the LOS threshold
on power-up is 2.2 V.
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POSITION REGISTER
Table 11. 16-Bit Register
Address
0x80
0x81
maximum velocity that the AD2S1210 can track for each
resolution is specified in Table 1. For example, the maximum
tracking rate of the AD2S1210 at 16 bits resolution, with an
8.192 MHz input clock, is ±125 rps. A velocity of +125 rps
results in 0x7FFF being stored in the velocity register; a velocity
of −125 rps results in 0x8000 being stored in the velocity register.
Bit
D15 to D8
D7 to D0
Read/Write
Read only
Read only
The position register contains a digital representation of the
angular position of the resolver input signals. The values are
stored in 16-bit binary format. The value in the position register
is updated following a falling edge on the SAMPLE input.
DOS OVERRANGE THRESHOLD REGISTER
Table 14. 8-Bit Register
Address
0x89
Bit
D7 to D0
Read/Write
Read/write
Note that with hysteresis enabled (see the Control Register
section), at lower resolutions, the LSBs of the 16-bit digital output
are set to zero. For example, at 10-bit resolution, Data Bit D15 to
Data Bit D6 provide valid data; D5 to D0 are set to zero. With
hysteresis disabled, the value stored in the position register is 16
bits regardless of resolution. At lower resolutions, the LSBs of
the 16-bit digital output can be ignored. For example, at 10-bit
resolution, Data Bit D15 to Data Bit D6 provide valid data; D5
to D0 can be ignored.
The DOS overrange threshold register determines the degradation
of signal threshold of the AD2S1210. The AD2S1210 allows the
user to set the DOS overrange threshold to a value between 0 V
and 4.82 V. The resolution of the DOS overrange threshold is
seven bits, that is, 38 mV. Note that the MSB, D7, should be set to
0. The default value of the DOS overrange threshold on power-up
is 4.1 V.
VELOCITY REGISTER
Table 15. 8-Bit Register
Table 12. 16-Bit Register
Address
0x8A
Address
0x82
0x83
Bit
D15 to D8
D7 to D0
Read/Write
Read only
Read only
The velocity register contains a digital representation of the angular
velocity of the resolver input signals. The value in the velocity
register is updated following a falling edge on the sample input.
The values are stored in 16-bit, twos complement format. The
DOS MISMATCH THRESHOLD REGISTER
Bit
D7 to D0
Read/Write
Read/write
The DOS mismatch threshold register determines the signal
mismatch threshold of the AD2S1210. The AD2S1210 allows
the user to set the DOS mismatch threshold to a value between
0 V and 4.82 V. The resolution of the DOS mismatch threshold
is seven bits, that is, 38 mV. Note that the MSB, D7, should be
set to 0.The default value of the DOS mismatch threshold on
power-up is 380 mV.
Rev. 0 | Page 21 of 36
AD2S1210
Table 19. LOT High/Low Threshold
DOS RESET MAXIMUM AND MINIMUM
THRESHOLD REGISTERS
Table 16. 8-Bit Registers
Address
0x8B
0x8C
Bit
D7 to D0
D7 to D0
Read/Write
Read/write
Read/write
The AD2S1210 continuously stores the minimum and maximum
magnitude of the monitor signal in internal registers. The difference between the minimum and maximum is calculated to
determine if a DOS mismatch has occurred. The initial values
for the minimum and maximum internal registers must be
defined by the user. When the fault register is cleared, the
registers that store the maximum and minimum amplitudes of
the monitor signal are reset to the values stored in the DOS reset
maximum and minimum threshold registers. The resolution of
the DOS reset maximum and minimum thresholds is seven bits
each, that is, 38 mV. Note that the MSB, D7, should be set to
0.To ensure correct operation, it is recommended that the DOS
reset minimum threshold register be set to at least 1 LSB less
than the DOS overrange threshold, and the DOS reset maximum
threshold register be set to at least 1 LSB greater than the LOS
threshold register. The default value of the DOS reset minimum
threshold register and the DOS reset maximum threshold
register are 3.99 V and 2.28 V, respectively.
Resolution
(Bits)
10
12
14
16
Range
(Degrees)
0 to 45
0 to 18
0 to 9
0 to 9
LOT Low
Default
(Degrees)
2.5
1.0
0.5
0.5
LSB Size
(Degrees)
0.35
0.14
0.09
0.09
LOT High
Default
(Degrees)
12.5
5.0
2.5
2.5
EXCITATION FREQUENCY REGISTER
Table 20. 8-Bit Register
Address
0x91
Bit
D7 to D0
Read/Write
Read/write
The excitation frequency register determines the frequency of
the excitation outputs of the AD2S1210. A 7-bit frequency control
word is written to the register to set the excitation frequency.
Note that the MSB, D7, should be set to 0.
(Excitation Frequency × 2 )
15
FCW =
f CLKIN
(9)
where FCW is the frequency control word and fCLKIN is the clock
frequency of the AD2S1210. The specified range of the excitation
frequency is from 2 kHz to 20 kHz and can be set in increments
of 250 Hz. To ensure that the AD2S1210 is operated within the
specified frequency range, the frequency control word should
be a value between 0x4 and 0x50.
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LOT HIGH THRESHOLD REGISTER
For example, if the user requires an excitation frequency of 5 kHz
and has an 8.192 MHz clock frequency, the code that needs to
be programmed is given by
Table 17. 8-Bit Register
Address
0x8D
Bit
D7 to D0
Read/Write
Read/write
The LOT high threshold register determines the loss of position
tracking threshold for the AD2S1210. The LOT high threshold
is a 7-bit word. Note that the MSB, D7, should be set to 0. The
range of the LOT high threshold, the LSB size, and the default
value of the LOT high threshold on power-up are dependent on
the resolution setting of the AD2S1210, and are outlined in
Table 19.
Table 18. 8-Bit Register
Bit
D7 to D0
8.192 MHz
= 14 (hexadecimal)
The default excitation frequency of the AD2S1210 on power-up
is 10 kHz.
CONTROL REGISTER
Table 21. 8-Bit Register
Address
0x92
LOT LOW THRESHOLD REGISTER
Address
0x8E
(5 kHz × 2 )
15
FCW =
Bit
D7 to D0
Read/Write
Read/write
The control register is an 8-bit register that sets the AD2S1210
control modes. The default value of the control register on
power-up is 0x7E.
Read/Write
Read/write
The LOT low threshold register determines the level of hysteresis
on the loss of position tracking fault detection. Loss of tracking
(LOT) occurs when the internal error signal of the AD2S1210
exceeds the LOT high threshold. LOT has hysteresis and is not
cleared until the internal error signal is less than the value defined
in the LOT low threshold register. The LOT low threshold is a
7-bit word. Note that the MSB, D7, should be set to 0. The range
of the LOT high threshold, the LSB size, and the default value of
the LOT high threshold on power-up are dependent on the resolution setting of the AD2S1210, and are outlined in Table 19.
Table 22. Control Register Bit Descriptions
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Rev. 0 | Page 22 of 36
Description
Address/data bit
Reserved; set to 1
Phase lock range
0 = 360°, 1 = ±44°
0 = disable hysteresis, 1 = enable hysteresis
Set Encoder Resolution EnRES1
Set Encoder Resolution EnRES0
Set Resolution RES1
Set Resolution RES0
AD2S1210
Address/Data Bit
Table 23. Encoder Resolution Settings
The MSB of each 8-bit word written to the AD2S1210 indicates
whether the 8-bit word is a register address or data. The MSB
(D7) of each register address defined on the AD2S1210 is high.
The MSB of each data word written to the AD2S1210 is low.
EnRES0
0
0
1
1
Note that when a data word is written to the AD2S1210, the
MSB is internally reconfigured as a parity bit. When reading
data from any of the read/write registers (see Table 10), the
parity of Bit D6 to Bit D0 is recalculated and compared to the
previously stored parity bit. The MSB of the 8-bit output is used
to indicate whether a configuration error has occurred. If the
MSB is returned high, this indicates that the data read back from
the device does not match the configuration data written to the
device in the previous write cycle.
Phase Lock Range
The phase lock range allows the AD2S1210 to compensate for
phase errors between the excitation frequency and the sine/cosine
inputs. The recommended mode of operation is to use the default
phase lock range of ±44°. If additional phase lock range is
required, a range of 360° can be set. However, in this mode of
operation, the AD2S1210 should be reset following a loss of
signal error. Failure to do so may result in a 180° error in the
angular output data.
EnRES1
0
1
0
1
Resolution (Bits)
10
12
14
16
Set Resolution
In normal mode, the resolution of the digital output is selected
using the RES0 and RES1 input pins (see Table 9). In
configuration mode, the resolution is selected by setting the
RES0 and RES1 bits in the control register. When switching
between normal mode and configuration mode, it is the
responsibility of the user to ensure that the resolution set in the
control register matches the resolution set by the RES0 and RES1
input pins. The default resolution of the digital output on powerup is 12 bits.
SOFTWARE RESET REGISTER
Table 24. 8-Bit Register
Address
0xF0
Bit
D7 to D0
Read/Write
Write only
Addressing the software reset register, that is writing the 8-bit
address, 0xF0, of the software reset register to the AD2S1210
while in configuration mode, allows the user to initiate a software reset of the AD2S1210. The software reset reinitializes the
excitation frequency outputs and the internal Type II tracking loop.
The data stored in the configuration registers is not overwritten
by a software reset. However, it should be noted that the data in
the fault register is reset. In an application that uses two or more
resolver-to-digital converters, which are both driven from the same
clock source, the software reset can be used to synchronize the
phase of the excitation frequencies across the converters.
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Hysteresis
The AD2S1210 includes a hysteresis function, ±1 LSB, between
the output of the position integrator and the input to the position
register. When operating in a noisy environment, this can be used
to prevent flicker on the LSB. On the AD2S1210, the maximum
tracking rate is defined by the bandwidth. Each resolution setting
is internally configured with a different bandwidth, as outlined
in Table 1. The maximum tracking rate and the bandwidth are
inversely proportional to the resolution, that is, the maximum
tracking rate increases as the resolution is decreased. The option
of disabling the hysteresis allows the user to oversample the
position output and to achieve a higher resolution output within
the specified bandwidths through external averaging.
The hysteresis function can be enabled or disabled through
setting Bit D4 in the control register. Hysteresis is enabled by
default on power-up.
Set Encoder Resolution
The resolution of the encoder outputs of the AD2S1210 can be
set to the same resolution as the digital output or it can also be
set to a lower resolution. For example, when the resolution of
the AD2S1210 position outputs is set to 16 bits, the resolution
of the encoder outputs may be set to 14, 12, or 10 bits. This
allows the user to take advantage of the lower bandwidth and
improved performance of the 16-bit resolution setting without
requiring external divide down of the A-quad-B encoder outputs.
The default resolution of the encoder outputs on power-up is 16
bits. Refer to the Incremental Encoder Outputs section.
FAULT REGISTER
Table 25. 8-Bit Register
Address
0xFF
Bit
D7 to D0
Read/Write
Read only
The AD2S1210 has the ability to detect eight separate fault conditions. When a fault occurs, the DOS and/or the LOT output
pins are taken low. By reading the fault register, the user can
determine the cause of the triggering of the fault detection output
pins. Note that the fault register bits are active high, that is, the
fault bits are taken high to indicate that a fault has occurred.
Table 26. Fault Register Bit Descriptions
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Rev. 0 | Page 23 of 36
Description
Sine/cosine inputs clipped
Sine/cosine inputs below LOS threshold
Sine/cosine inputs exceed DOS overrange threshold
Sine/cosine inputs exceed DOS mismatch threshold
Tracking error exceeds LOT threshold
Velocity exceeds maximum tracking rate
Phase error exceeds phase lock range
Configuration parity error
AD2S1210
DIGITAL INTERFACE
The angular position and angular velocity are represented by
binary data and can be extracted either via a 16-bit parallel
interface or via a 4-wire serial interface that operates at clock
rates of up to 25 MHz. The AD2S1210 programmable functions
are controlled using a set of on-chip registers. Data is written to
these registers using either the serial or the parallel interface.
SOE INPUT
The serial output enable pin, SOE, is held high to enable the
parallel interface. The SOE pin is held low to enable the serial
interface, which places Pin DB0 to Pin DB12 in the high impedance state. Pin DB13 is the serial clock input (SCLK), Pin DB14
is the serial data input (SDI), Pin DB15 is the serial data output
(SDO), and WR/FSYNC is the frame synchronization input.
SAMPLE INPUT
The AD2S1210 operates on a Type II tracking closed-loop
principle. The loop continually tracks the position and velocity
of the resolver without the need for external conversion and
wait states. The position and velocity registers are external to
the loop and are updated with a high-to-low transition of the
SAMPLE signal. This pin must be held low for at least t16 ns
to guarantee correct latching of the data.
Reading from the AD2S1210
The following data can be read back from the AD2S1210:
•
•
•
•
Angular position
Angular velocity
Fault register data
Status of on-chip registers
The angular position and angular velocity data can be read back
in either normal mode or configuration mode. To read the
status of the fault register or the remaining on-chip registers,
the part must be put into configuration mode.
Reading from the AD2S1210 in Configuration Mode
To read back data stored in one of the on-chip registers, including
the fault register, the user must first place the AD2S1210 into
configuration mode using the A0 and A1 inputs. The 8-bit address
of the register to be read should then be written to the part, as
described in the Writing to the AD2S1210 section. This transfers
the relevant data to the output register. The data can then be
read using the RD input as described previously. When reading
back data from any of the read/write registers (see Table 10), the
8-bit word consists of the seven bits of data in the relevant register,
D6 to D0, and an error bit, D7. If the error bit is returned high,
this indicates that the data read back from the device does not
match the configuration data written to the device in the previous
write cycle.
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DATA FORMAT
The digital angle data represents the absolute position of the
resolver shaft as a 10-bit to 16-bit unsigned binary word. The
digital velocity data is a 10-bit to 16-bit twos complement word,
which represents the velocity of the resolver shaft rotating in
either a clockwise or a counterclockwise direction.
The parallel interface is selected holding the SOE pin high. The
chip select pin, CS, must be held low to enable the interface.
If the user wants to read back the angular position or velocity
data while in configuration mode, a falling edge of the SAMPLE
input is required to update the information in the position and
velocity registers. The data in these registers can then be read back
by addressing the required register and reading back the data as
described previously. Figure 29 shows the timing specifications to
follow when reading from the configuration registers.
Writing to the AD2S1210
Reading from the AD2S1210 in Normal Mode
The on-chip registers of the AD2S1210 are written to, in parallel
mode, using an 8-bit parallel interface, D7 to D0, and the WR/
FSYNC pin. The MSB of each 8-bit word written to the AD2S1210
indicates whether the 8-bit word is a register address or data.
The MSB (D7) of each register address defined on the AD2S1210
is high (see the Register Map section). The MSB of each data
word written to the AD2S1210 is low. To write to one of the
registers, the user must first place the AD2S1210 into configuration mode using the A0 and A1 inputs. Then the 8-bit address
should be written to the AD2S1210 using Pin DB7 to Pin DB0,
and latched using the rising edge of the WR/FSYNC input. The
data can then be presented on Pin DB7 to Pin DB0 and again
latched into the part using the WR/FSYNC input. Figure 28 shows
the timing specifications to follow when writng to the configuration registers. Note that the RD input should be held high when
writing to the AD2S1210.
To read back position or velocity data from the AD2S1210, the
information stored in the position and velocity registers should
first be updated using the SAMPLE input. A high-to-low transition
on the SAMPLE input transfers the data from the position and
velocity integrators to the position and velocity registers. The
fault register is also updated on the high-to-low transition of the
SAMPLE input. The status of the A0 and A1 inputs determines
whether the position or velocity data is transferred to the output
register. The CS pin must be held low to transfer the selected
data to the output register. Finally, the RD input is used to read
the data from the output register and to enable the output buffer.
The output buffer is enabled when CS and RD are held low. The
data pins return to a high impedance state when RD returns to
a high state. If the user is reading data continuously, RD can be
reapplied a minimum of t20 ns after it was released.
PARALLEL INTERFACE
The timing requirements for the read cycle are shown in Figure 30.
Note that the WR/FSYNC input should be high when RD is low.
Rev. 0 | Page 24 of 36
AD2S1210
Clearing the Fault Register
4.
The LOT pin and/or the DOS pin of the AD2S1210 are taken
low to indicate that a fault has been detected. The AD2S1210 is
capable of detecting eight separate fault conditions. To determine
which condition triggered the fault indication, the user is required
to enter configuration mode and read the fault register. To reset
the fault indicators, an additional SAMPLE pulse is required.
This ensures that any faults that may occur between the initial
sampling and subsequent reading of the fault register are captured.
Therefore, to read and clear the fault register, the following
sequence of events is required:
3.
6.
Figure 31 shows the timing specifications to follow when
clearing the fault register.
Note that the last valid register address written to the AD2S1210
prior to exiting configuration mode is again valid when reentering
configuration mode. It is therefore recommended that when
initial configuration of the AD2S1210 is complete, the fault address
should be written to the AD2S1210 before leaving configuration
mode. This simplifies the reading and clearing of the fault register
in normal operation because it is now possible to access the
position, velocity, and fault information by toggling the A0 and
A1 pins without requiring additional register addressing.
A high-to-low transition of the SAMPLE input.
The SAMPLE input should be held low for t16 ns and then
can be returned high.
The AD2S1210 should be put into configuration mode,
that is, A0 and A1 are both set to logic high.
fCLKIN
CLKIN
t8
t1
A0, A1
t1
t6
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CS
t2
t5
t2
t2
t9
t7
WR
t3
DB0 TO DB7
t4
ADDRESS
t3
t4
DATA
NOTES
1.
DON’T CARE.
2. RD SHOULD BE HELD HIGH WHEN WRITING TO THE AD2S1210.
Figure 28. Parallel Port Write Timing—Configuration Mode
Rev. 0 | Page 25 of 36
ADDRESS
07467-027
1.
2.
5.
The fault register should be read as described in the
Reading from the AD2S1210 in Configuration Mode
section.
A second high-to-low transition of the SAMPLE input
clears the fault indications on the DOS and/or LOT pins.
Note that in the event of a persistent fault, the fault indicators are reasserted within the specified fault time latency.
AD2S1210
fCLKIN
CLKIN
t1
A0, A1
t2
t14B
t11
CS
t5
t13
t15
WR
t12
t10
RD
t14A
t14A
t4
t12
t3
DB0 TO DB7
ADDRESS
DATA
ADDRESS
DATA
07467-028
NOTES
1.
DON’T CARE.
Figure 29. Parallel Port Read Timing—Configuration Mode
fCLKIN
CLKIN
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t16
t16
SAMPLE
t17
t6
CS
t18
t20
RD
t1
POSITION
t19
DATA
POSITION
FAULT*
VELOCITY
t14A/t14B
t21
VELOCITY
FAULT*
*ASSUMES FAULT REGISTER ADDRESS WRITTEN TO PART BEFORE EXITING CONFIGURATION MODE.
NOTES
1.
DON’T CARE.
Figure 30. Parallel Port Read Timing
Rev. 0 | Page 26 of 36
07467-029
A0, A1
AD2S1210
fCLKIN
CLKIN
t16
t16
t16
SAMPLE
t17
CS
t2
WR
t9
RD
t1
CONFIGURATION
t3
DATA
t12
t4
t14A
t19
FAULT ADDRESS
FAULT DATA
NOTES
1.
DON’T CARE.
Figure 31. Parallel Port—Clear Fault Register
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Rev. 0 | Page 27 of 36
07467-030
A0, A1
AD2S1210
SERIAL INTERFACE
The serial interface is selected by holding the SOE pin low. The
AD2S1210 serial interface consists of four signals: SDO, SDI,
WR/FSYNC, and SCLK. The SDI is used for transferring data
into the on-chip registers whereas the SDO is used for accessing
data from the on-chip registers, including the position, velocity,
and fault registers. SCLK is the serial clock input for the device,
and all data transfers (either on SDI or SDO) take place with
respect to this SCLK signal. WR/FSYNC is used to frame the
data. The falling edge of WR/FSYNC takes the SDI and SDO
lines out of a high impedance state. A rising edge on WR/FSYNC
returns the SDI and SDO to a high impedance state. The CS input
is not required for the serial interface and should be held low.
SDO Output
In normal mode of operation, data is shifted out of the device as
a 24-bit word under the control of the serial clock input, SCLK.
The data is shifted out on the rising edge of SCLK. The timing
diagram for this operation is shown in Figure 32.
SDI Input
The SDI input is used to address the on-chip registers and as a
daisy-chain input in configuration mode. The data is shifted
into the part on the falling edge of SCLK. The timing diagram
for this operation is shown in Figure 32.
this indicates that the data read back from the device does not
match the configuration data written to the device in the previous
write cycle.
To read back the angular position or velocity data while in
configuration mode, a falling edge of the SAMPLE input is
required to update the information in the position and velocity
registers.
Reading from the AD2S1210 in Normal Mode
To read back position or velocity data from the AD2S1210, the
information stored in the position and velocity registers should
first be updated using the SAMPLE input. A high-to-low
transition on the SAMPLE input transfers the data from the
position and velocity integrators to the position and velocity
registers. The fault register is also updated on the high-to-low
transition of the SAMPLE input. The status of the A0 and A1
inputs determines whether the position or velocity data is
transferred to the output register.
In normal mode, the output shift register is 24 bits wide. The 24-bit
word consists of 16 bits of angular data (position or velocity data)
followed by the 8-bit fault register data. Data is read out MSB
first (Bit 23) on the SDO pin. Bit 23 through Bit 8 correspond to
the angular information. The angular position data format is
unsigned binary, with all 0s corresponding to 0 degrees and all
1s corresponding to 360 degrees − l LSB. The angular velocity data
format is twos complement binary, with the MSB representing the
rotation direction. Bit 7 through Bit 0 correspond to the fault
information. If the user does not require the fault information,
the WR/FSYNC can be pulled high after the16th SCLK rising edge.
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Writing to the AD2S1210
The on-chip registers of the AD2S1210 can be accessed using
the serial interface. To write to one of the registers, the user
must first place the AD2S1210 into configuration mode using
the A0 and A1 inputs. The 8-bit address should be written to
the AD2S1210 using the SDI pin and latched using the rising
edge of the WR/FSYNC input. The data can then be presented on
the SDI pin and again latched into the part using the WR/FSYNC
input. The MSB of the 8-bit write indicates whether the 8-bit
word is a register address, MSB set high, or the data to be written,
MSB set low. Figure 33 shows the timing specifications to follow
when writing to the configuration registers.
Reading from the AD2S1210 in Configuration Mode
To read back data stored in one of the on-chip registers, including
the fault register, the user must first place the AD2S1210 into
configuration mode using the A0 and A1 inputs. The 8-bit
address of the register to be read should then be written to the
part, as described in the Writing to the AD2S1210 section.
This transfers the relevant data to the output register.
In configuration mode, the output shift register is eight bits
wide. Data is shifted out of the device as an 8-bit word under
the control of the serial clock input, SCLK. The timing diagram
for this operation is shown in Figure 34. When reading back
data from any of the read/write registers (see Table 10), the 8-bit
word consists of the seven bits of data in the relevant register,
D6 to D0, and an error bit, D7. If the error bit is returned high,
Clearing the Fault Register
The LOT pin and/or the DOS pin of the AD2S1210 are taken
low to indicate that a fault has been detected. The AD2S1210 is
capable of detecting eight separate fault conditions. To determine
which condition triggered the fault indication, the user is required
to enter configuration mode and read the fault register. To reset
the fault indicators, an additional SAMPLE pulse is required.
This ensures that any faults that may occur between the initial
sampling and subsequent reading of the fault register are captured.
Therefore, to read and clear the fault register, the following
sequence of events is required:
1.
2.
3.
4.
5.
Rev. 0 | Page 28 of 36
A high-to-low transition of the SAMPLE input.
Hold the SAMPLE input low for t16 ns and then it can be
returned high.
Put the AD2S1210 into configuration mode, that is, A0 and
A1 are both set to logic high.
Read the fault register as described in the Reading from the
AD2S1210 in Configuration Mode section.
A second high-to-low transition of the SAMPLE input
clears the fault indications on the DOS and/or LOT pins.
Note that in the event of a persistent fault, the fault indicators
are reasserted within the specified fault time latency.
AD2S1210
WR/FSYNC
t22
t 29
fSCLK
t25
SCLK
t23
t24
t26
MSB
LSB
t27
t28
MSB
SDI
07467-031
SDO
LSB
Figure 32. Serial Interface Timing Diagram
fCLKIN
CLKIN
t1
t1
t8
A0, A1
t5
t2
CS
t2
t7
t9
WR/FSYNC
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SDI
ADDRESS
DATA
NEW ADDRESS
OLD DATA
OLD DATA
COPY OF DATA
NOTES
1.
DON’T CARE.
07467-032
SDO
Figure 33. Serial Interface Write Timing—Configuration Mode
fCLKIN
CLKIN
A0, A1
t1
t5
t6
t2
t5
CS
t2
WR/FSYNC
ADDRESS 1
ADDRESS 2
ADDRESS 3
SDO
OLD DATA
DATA 1
DATA 2
07467-033
SDI
NOTES
1.
DON’T CARE.
Figure 34. Serial Interface Read Timing—Configuration Mode
Rev. 0 | Page 29 of 36
AD2S1210
fCLKIN
CLKIN
t16
t16
SAMPLE
t30
t6
CS
t31
t34
WR/FSYNC
t32
A0, A1
t33
POSITION
VELOCITY
FAULT*
t29
t23
SDO
POSITION
VELOCITY
FAULT*
07467-034
*ASSUMES FAULT REGISTER ADDRESS WRITTEN TO PART BEFORE EXITING CONFIGURATION MODE.
NOTES
1.
DON’T CARE.
Figure 35. Serial Interface Read Timing
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Rev. 0 | Page 30 of 36
AD2S1210
INCREMENTAL ENCODER OUTPUTS
SUPPLY SEQUENCING AND RESET
The A, B, and NM incremental encoder emulation outputs are
free running and are valid if the resolver format input signals
applied to the converter are valid.
The AD2S1210 requires an external reset signal to hold the
RESET input low until VDD is within the specified operating
range of 4.5 V to 5.5 V.
The AD2S1210 can be configured to emulate a 256-line, a
1024-line, a 4096-line, or a 16,384-line encoder. For example,
if the AD2S1210 is configured for 12-bit resolution, one revolution produces 1024 A and B pulses. Pulse A leads Pulse B for
increasing angular rotation (that is, clockwise direction).
The RESET pin must be held low for a minimum of 10 μs after
VDD is within the specified range (shown as tRST in Figure 37).
Applying a RESET signal to the AD2S1210 initializes the output
position to a value of 0x000 (degrees output through the parallel,
serial, and encoder interfaces) and causes LOS to be indicated
(LOT and DOS pins pulled low), as shown in Figure 37.
The resolution of the encoder emulation outputs of the AD2S1210
is generally configured to match the resolution of the digital output.
However, the encoder emulation outputs of the AD2S1210 can also
be configured to have a lower resolution than the digital outputs.
For example, if the AD2S1210 is configured for 16-bit resolution, then the encoder emulation outputs can also be configured
for 14-bit, 12-bit, or 10-bit resolution. However, the resolution
of the encoder emulation outputs cannot be higher than the
resolution of the digital output. If the AD2S1210 is configured
such that the resolution of the encoder emulation outputs is
higher than the resolution of the digital outputs, the AD2S1210
internally overrides this configuration. In this event, the resolution of the encoder outputs is set to match the resolution of the
digital outputs. The resolution of the encoder emulation outputs
can be programmed by writing to Bit D3 and Bit D2 of the
control register.
Failure to apply the correct power-up/reset sequence may result
in an incorrect position indication.
After a rising edge on the RESET input, the device must be allowed
at least tTRACK ms (see Figure 37) for the internal circuitry to stabilize and the tracking loop to settle to the step change of the input
position. For the duration of tTRACK fault indications may occur
on the LOT and DOS pins due to the step response caused by
the RESET. The duration of tTRACK is dependent on the converter
resolution as outlined in Table 27. After tTRACK, the fault register
should be read and cleared as outlined in the Clearing the Fault
Register section. The time required to read and clear the fault
register is indicated as tFAULT, and is defined by the interface
speed of the DSP/microprocessor used in the application. (Note
that if position data is acquired via the encoder outputs, these
can be monitored during tTRACK.)
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The north marker pulse is generated as the absolute angular
position passes through zero. The north marker pulse width
is set internally for 90° and is defined relative to the A cycle.
Figure 36 details the relationship between A, B, and NM.
Table 27. tTRACK vs. Resolution (fCLKIN = 8.192 MHz)
Resolution (Bits)
10
12
14
16
A
VDD
B
tTRACK (ms)
10
20
25
60
4.75V
tRST
07467-035
RESET
tFAULT
SAMPLE
Figure 36. A, B, and NM Timing for Clockwise Rotation
The inclusion of A and B outputs allows the AD2S1210 with
resolver solution to replace optical encoders directly without
the need to change or upgrade existing application software.
LOT
VALID
OUTPUT
DATA
DOS
Figure 37. Power Supply Sequencing and Reset
Rev. 0 | Page 31 of 36
07457-036
NM
tTRACK
AD2S1210
CIRCUIT DYNAMICS
RDC closed-loop transfer function
LOOP RESPONSE MODEL
θIN
k1 × k2
–
c
1 – z–1
H (z ) =
VELOCITY
1 – az–1
1 – bz–1
c
1 – z–1
θOUT
07467-037
ERROR
(ACCELERATION)
Sin/Cos LOOKUP
Figure 38. RDC System Response Block Diagram
The following equations outline the transfer functions of the
individual blocks as shown in Figure 38, which then combine to
form the complete RDC system loop response.
(13)
The closed-loop magnitude and phase responses are that of a
second-order low-pass filter (see Figure 11 and Figure 12).
To convert G(z) into the s-plane, an inverse bilinear transformation is performed by substituting the following equation for z:
2
+s
z= t
2
−s
t
The RDC is a mixed-signal device that uses two ADCs to digitize
signals from the resolver and a Type II tracking loop to convert
these to digital position and velocity words.
The first gain stage consists of the ADC gain on the sine/cosine
inputs and the gain of the error signal into the first integrator.
The first integrator generates a signal proportional to velocity.
The compensation filter contains a pole and a zero that are used
to provide phase margin and reduce high frequency noise gain.
The second integrator is the same as the first and generates the
position output from the velocity signal. The sin/cos lookup has
unity gain. The values for the k1, k2, a, b, and c parameters are
outlined in Table 28.
G( z )
1 + G( z )
(14)
where t is the sampling period (1/4.096 MHz ≈ 244 ns).
Substitution yields the open-loop transfer function, G(s).
G( s ) =
k1 × k2(1 − a)
×
a −b
s 2t 2 1 + s × t (1 + a)
2(1 − a)
4 ×
t (1 + b)
s2
1+ s×
2(1 − b)
1 + st +
This transformation produces the best matching at low frequencies
(f < fSAMPLE). At such frequencies (within the closed-loop
bandwidth of the AD2S1210), the transfer function can be
simplified to
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G( s ) ≅
Integrator1 and Integrator2 transfer function
c
I (z ) =
1 − z −1
(10)
1 − az −1
1 − bz −1
t1 =
(11)
t2 =
RDC open-loop transfer function
G(z ) = k1 × k2 × I (z ) 2 × C(z )
K a 1 + st1
×
s 2 1 + st 2
(16)
where:
Compensation filter transfer function
C (z ) =
(15)
t (1 + a)
2(1 − a)
t (1 + b)
2(1 − b)
Ka =
(12)
k1 × k2(1 − a)
a −b
Solving for each value gives t1, t2, and Ka as outlined in Table 29.
Table 28. RDC System Response Parameters
Parameter
k1 (nominal)
k2
a
b
c
Description
ADC gain
Error gain
Compensator zero coefficient
Compensator pole coefficient
Integrator gain
10-bit resolution
1.8/2.5
6 × 106 × 2π
8187/8192
509/512
1/1,024,000
12-bit resolution
1.8/2.5
18 × 106 × 2π
4095/4096
4085/4096
1/4,096,000
Rev. 0 | Page 32 of 36
14-bit resolution
1.8/2.5
82 x 106 × 2π
8191/8192
16,359/16,384
1/16,384,000
16-bit resolution
1.8/2.5
66 × 106 × 2π
32,767/32,768
32,757/32,768
1/65,536,000
AD2S1210
Table 29. Loop Transfer Function Parameters vs. Resolution
(fCLKIN = 8.192 MHz)
Resolution (Bits)
10
12
14
16
t1 (ms)
0.4
1
2
8
t2 (ms)
42
91
160
728
−2
Ka (sec )
39.6 × 106
6.5 × 106
1.6 × 106
92.7 × 103
SOURCES OF ERROR
Acceleration
A tracking converter employing a Type II servo loop does not
have a lag in velocity. There is, however, an error associated
with acceleration. This error can be quantified using the
acceleration constant (Ka) of the converter.
Ka =
Note that the closed-loop response is described as
H (s ) =
G( s )
1 + G( s )
(17)
By converting the calculation to the s-domain, it is possible to
quantify the open-loop dc gain (Ka). This value is useful to
calculate the acceleration error of the loop (see the Sources of
Error section).
The step response to a 10° input step is shown in Figure 10,
Figure 11, Figure 12, and Figure 13. The step response to a 179°
input step is shown in Figure 14, Figure 15, Figure 16, and
Figure 17. In response to a step change in velocity, the
AD2S1210 exhibits the same response characteristics as it does
for a step change in position.
Figure 18 and Figure 19 in the Typical Performance
Characteristics section show the magnitude and phase responses
of the AD2S1210 for each resolution setting.
Input Acceleration
(18)
Tracking Error
Conversely,
Tracking Error =
Input Acceleration
Ka
(19)
The units of the numerator and denominator must be consistent.
The maximum acceleration of the AD2S1210 is defined by the
maximum acceptable tracking error in the users application.
For example, if the maximum acceptable tracking error is 5°,
then the maximum acceleration is defined as the acceleration that
creates an output position error of 5° (that is, when LOT is
indicated).
An example of how to calculate the maximum acceleration in a
12-bit application with a maximum tracking error of 5° is
Maximum Acceleration =
K a (sec−2 ) × 5°
≅ 90,300 rps2
360(°/rev )
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Figure 20 to Figure 23 in the Typical Performance
Characteristics section show the tracking error vs. acceleration
response of the AD2S1210 for each resolution setting.
Rev. 0 | Page 33 of 36
(20)
AD2S1210
OUTLINE DIMENSIONS
9.20
9.00 SQ
8.80
1.60
MAX
37
48
36
1
PIN 1
0.15
0.05
7.20
7.00 SQ
6.80
TOP VIEW
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
SEATING
PLANE
VIEW A
(PINS DOWN)
25
12
13
VIEW A
0.50
BSC
LEAD PITCH
24
0.27
0.22
0.17
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
051706-A
0.75
0.60
0.45
Figure 39. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD2S1210ASTZ1
AD2S1210BSTZ1
AD2S1210CSTZ1
AD2S1210DSTZ1
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
Package Description
48-Lead LQFP
48-Lead LQFP
48-Lead LQFP
48-Lead LQFP
Package Option
ST-48
ST-48
ST-48
ST-48
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Z = RoHS Compliant Part.
Rev. 0 | Page 34 of 36
AD2S1210
NOTES
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Rev. 0 | Page 35 of 36
AD2S1210
NOTES
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©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07467-0-8/08(0)
Rev. 0 | Page 36 of 36
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