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AD5235 数据手册DataSheet下载
Nonvolatile Memory, Dual
1024-Position Digital Potentiometer
AD5235
FEATURES
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS
DWDM laser diode driver, optical supervisory systems
Mechanical potentiometer replacement
Instrumentation: gain, offset adjustment
Programmable voltage to current conversion
Programmable filters, delays, time constants
Programmable power supply
Low resolution DAC replacement
Sensor calibration
CS
AD5235
ADDR
DECODE
RDAC1
REGISTER
A1
W1
CLK
SDI
SERIAL
INTERFACE
SDO
PR
WP
RDY
EEMEM1
POWER-ON
RESET
VDD
RDAC1
RDAC2
REGISTER
B1
A2
W2
EEMEM
CONTROL
B2
EEMEM2
RTOL3
RDAC2
26 BYTES
USER EEMEM
VSS
GND
02816-B-001
Dual-channel, 1024-position resolution
25 kΩ, 250 kΩ nominal resistance
Low temperature coefficient: 35 ppm/°C
Nonvolatile memory stores wiper settings
Permanent memory write protection
Wiper setting readback
Resistance tolerance stored in EEMEM
Predefined linear increment/decrement instructions
Predefined ±6 dB/step log taper increment/decrement
instructions
SPI® compatible serial interface
3 V to 5 V single supply or ±2.5 V dual supply
26 bytes extra nonvolatile memory for user-defined
information
100-year typical data retention, TA = 55°C
Power-on refreshed with EEMEM settings
Figure 1.
In the scratchpad programming mode, a specific setting can be
programmed directly to the RDAC2 register, which sets the
resistance between Terminals W–A and W–B. This setting can
be stored into the EEMEM and is restored automatically to the
RDAC register during system power-on.
www.BDTIC.com/ADI
GENERAL DESCRIPTION
The AD5235 is a dual-channel, nonvolatile memory,1 digitally
controlled potentiometer2 with 1024-step resolution. The device
performs the same electronic adjustment function as a
mechanical potentiometer with enhanced resolution, solid state
reliability, and superior low temperature coefficient performance. The AD5235’s versatile programming via an SPI
compatible serial interface allows 16 modes of operation and
adjustment including scratchpad programming, memory
storing and restoring, increment/decrement, ±6 dB/step log
taper adjustment, wiper setting readback, and extra EEMEM for
user-defined information such as memory data for other
components, look-up table, or system identification
information.
The EEMEM content can be restored dynamically or through
external PR strobing, and a WP function protects EEMEM
contents. To simplify the programming, the independent or
simultaneous linear-step increment or decrement commands
can be used to move the RDAC wiper up or down, one step at a
time. For logarithmic ±6 dB changes in wiper setting, the left or
right bit shift command can be used to double or half the
RDAC wiper setting.
AD5235 patterned resistance tolerance is stored in the EEMEM.
The actual end-to-end resistance can, therefore, be known by
the host processor in readback mode. The host can execute the
appropriate resistance step through a software routine that
simplifies open-loop applications as well as precision calibration
and tolerance matching applications.
The AD5235 is available in a thin TSSOP-16 package. The part
is guaranteed to operate over the extended industrial temperature range of −40°C to +85°C.
1
The terms nonvolatile memory and EEMEM are used interchangeably.
The terms digital potentiometer and RDAC are used interchangeably.
3
RAB tolerance.
2
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD5235
TABLE OF CONTENTS
Specifications..................................................................................... 3
AD5235EVAL Evaluation Kit ................................................... 21
Electrical Characteristics—25 kΩ, 250 kΩ Versions................ 3
Applications..................................................................................... 22
Interface Timing Characteristics—25 kΩ, 250 kΩ Versions... 5
Bipolar Operation from Dual Supplies.................................... 22
Timing Diagrams.......................................................................... 6
Gain Control Compensation .................................................... 22
Absolute Maximum Ratings............................................................ 7
High Voltage Operation............................................................. 22
ESD Caution.................................................................................. 7
DAC.............................................................................................. 22
Pin Configuration and Function Descriptions............................. 8
Bipolar Programmable Gain Amplifier................................... 23
Typical Performance Characteristics ............................................. 9
10-Bit Bipolar DAC.................................................................... 23
Test Circuits................................................................................. 12
Programmable Voltage Source with Boosted Output............ 23
Theory of Operation ...................................................................... 14
Programmable Current Source ................................................ 24
Scratchpad and EEMEM Programming.................................. 14
Programmable Bidirectional Current Source......................... 24
Basic Operation .......................................................................... 14
Programmable Low-Pass Filter ................................................ 24
EEMEM Protection.................................................................... 15
Programmable Oscillator .......................................................... 25
Digital Input/Output Configuration........................................ 15
Optical Transmitter Calibration with ADN2841 ................... 25
Serial Data Interface................................................................... 15
Resistance Scaling ...................................................................... 26
Daisy-Chain Operation ............................................................. 15
Resistance Tolerance, Drift, and Temperature Coefficient
Mismatch Considerations ......................................................... 26
www.BDTIC.com/ADI
Terminal Voltage Operating Range.......................................... 16
Advanced Control Modes ......................................................... 18
RDAC Structure.......................................................................... 19
Programming the Variable Resistor ......................................... 20
RDAC Circuit Simulation Model ............................................. 27
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 28
Programming the Potentiometer Divider ............................... 20
Programming Examples ............................................................ 21
REVISION HISTORY
7/04—Data Sheet Changed from REV. A to REV. B
Updated Formatting ........................................................... Universal
Edits to Theory of Operation.........................................................14
Edits to Features, General Description, and Block Diagram .......1
Edits to Applications .......................................................................23
Changes to Specifications .................................................................3
Updated Outline Dimensions........................................................27
Replaced Timing Diagrams..............................................................6
8/02—Data Sheet Changed from REV. 0 to REV. A
Changes to Absolute Maximum Ratings ........................................7
Change to Features and General Description................................1
Changes to Pin Function Descriptions...........................................8
Change to Specifications ..................................................................2
Changes to Typical Performance Characteristics..........................9
Change to Calculating Actual End-to-End Terminal
Resistance Section ..........................................................................14
Additional Test Circuit (Figure 36) .................................................9
Rev.B | Page 2 of 28
AD5235
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—25 KΩ, 250 KΩ VERSIONS
VDD = 3 V to 5.5 V, VSS = 0 V, VA = VDD, VB = 0 V, −40°C < TA < +85°C, unless otherwise noted.
The part can be operated at 2.7 V single supply, except from 0°C to −40°C, where a minimum of 3 V is needed.
Table 1.
Parameter
Symbol
DC CHARACTERISTICS— RHEOSTAT MODE (All RDACs)
Resistor Differential Nonlinearity2
R-DNL
Resistor Integral Nonlinearity2
R-INL
Nominal Resistor Tolerance
∆RAB/RAB
Resistance Temperature Coefficient
(∆RAB/RAB)/∆T × 106
Wiper Resistance
RW
Conditions
Min
RWB
RWB
Dx = 0x3FF
−2
−4
−30
IW = 1 V/RWB, VDD = 5 V,
Code = 0x200
IW = 1 V/RWB, VDD = 3 V,
Code = 0x200
Channel Resistance Matching
RAB1/RAB2
Ch 1 and 2 RWB, Dx = 0x3FF
DC CHARACTERISTICS— POTENTIOMETER DIVIDER MODE (All RDACs)
Resolution
N
Differential Nonlinearity3
DNL
Integral Nonlinearity3
INL
(∆VW/VW)/∆T × 106
Code = half-scale
Voltage Divider Temperature
Coefficient
Full-Scale Error
VWFSE
Code = full scale
Zero-Scale Error
VWZSE
Code = zero scale
RESISTOR TERMINALS
Terminal Voltage Range4
VA, B, W
5
Capacitance Ax, Bx
CA, B
f = 1 MHz, measured to GND,
Code = half-scale
Capacitance5 Wx
CW
f = 1 MHz, measured to GND,
Code = half-scale
Common-Mode Leakage Current5 , 6
ICM
VW = VDD/2
DIGITAL INPUTS AND OUTPUTS
Input Logic High
VIH
With respect to GND, VDD = 5 V
Input Logic Low
VIL
With respect to GND, VDD = 5 V
Input Logic High
VIH
With respect to GND, VDD = 3 V
Input Logic Low
VIL
With respect to GND, VDD = 3 V
Input Logic High
VIH
With respect to GND, VDD =
+2.5 V, VSS = −2.5 V
Input Logic Low
VIL
With respect to GND, VDD =
+2.5 V, VSS = −2.5 V
Output Logic High (SDO, RDY)
VOH
RPULL-UP = 2.2 kΩ to 5 V
(see Figure 25)
Output Logic Low
VOL
IOL = 1.6 mA, VLOGIC = 5 V
(see Figure 25)
Input Current
IIL
VIN = 0 V or VDD
Input Capacitance5
CIL
POWER SUPPLIES
Single-Supply Power Range
VDD
VSS = 0 V
Dual-Supply Power Range
VDD/VSS
Positive Supply Current
IDD
VIH = VDD or VIL = GND, TA = 25°C
IDD
VIH = VDD or VIL = GND
Negative Supply Current
ISS
VIH = VDD or VIL = GND,
VDD = +2.5 V, VSS = −2.5 V
Typ1
35
50
Max
Unit
+2
+4
+30
LSB
LSB
%
ppm/°C
Ω
100
200
Ω
±0.1
%
10
+2
+4
Bits
LSB
LSB
ppm/°C
−6
0
0
4
LSB
LSB
VSS
VDD
11
V
pF
80
pF
−2
−4
15
www.BDTIC.com/ADI
Rev. B | Page 3 of 28
0.01
±2
2.4
0.8
2.1
0.6
2.0
0.5
4.9
µA
V
V
V
V
V
V
V
0.4
V
±2.25
µA
pF
5.5
±2.75
4.5
6.0
6.0
V
V
µA
µA
µA
5
3.0
±2.25
2
3.5
3.5
AD5235
Parameter
EEMEM Store Mode Current
Symbol
IDD (store)
7
EEMEM Restore Mode Current
Power Dissipation8
Power Supply Sensitivity5
DYNAMIC CHARACTERISTICS5, 9
Bandwidth
1
ISS (store)
IDD (restore)
ISS (restore)
PDISS
PSS
BW
Total Harmonic Distortion
THDW
VW Settling Time
tS
Resistor Noise Density
Crosstalk (CW1/CW2)
eN_WB
CT
Analog Crosstalk
CTA
Conditions
VIH = VDD or VIL = GND,
VSS = GND, ISS ≈ 0
VDD = +2.5 V, VSS = −2.5 V
VIH = VDD or VIL = GND,
VSS = GND, ISS ≈ 0
VDD = +2.5 V, VSS = −2.5 V
VIH = VDD or VIL = GND
∆VDD = 5 V ± 10%
−3 dB, VDD/VSS = ±2.5 V,
RAB = 25 kΩ/250 kΩ
VA = 1 V rms, VB = 0 V, f = 1 kHz
VA = 1 V rms, VB = 0 V, f = 1 kHz,
RAB = 50 kΩ, 100 kΩ
VA = VDD, VB = 0 V,
VW = 0.50% error band,
Code 0x000 to 0x200,
RAB = 25 kΩ/250 kΩ
RAB = 25 kΩ/250 kΩ, TA = 25°C
VA = VDD, VB = 0 V, measured VW1
with VW2 making full-scale
change
VDD = VA1 = +2.5 V, VSS = VB1 =
−2.5 V, measured VW1with VW2 =
5 V p-p @ f = 1 kHz, Code 1 =
0x200, Code 2 = 0x3FF,
RAB = 25 kΩ/250 kΩ
Min
0.3
−0.3
Typ1
35
Max
Unit
mA
−35
3
9
mA
mA
−3
18
0.002
−9
50
0.01
mA
µW
%/%
125/12
kHz
0.05
0.045
%
%
4/36
µs
20/64
90/21
nV/√Hz
nV-s
−81/−62
dB
www.BDTIC.com/ADI
Typicals represent average readings at 25°C and VDD = 5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. IW ~ 50 µA for VDD = 2.7 V and IW ~ 400 µA for VDD = 5 V (see Figure 25).
3
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = VSS. DNL specification limits of
±1 LSB maximum are guaranteed monotonic operating conditions (see Figure 26).
4
Resistor Terminals A, B, and W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-referenced bipolar signal adjustment.
5
Guaranteed by design and not subject to production test.
6
Common-mode leakage current is a measure of the dc leakage from any Terminal B–W to a common-mode bias level of VDD/2.
7
EEMEM restore mode current is not continuous. Current consumed while EEMEM locations are read and transferred to the RDAC register (see Figure 22). To minimize
power dissipation, a NOP, Instruction 0 (0x0) should be issued immediately after Instruction 1 (0x1).
8
PDISS is calculated from (IDD × VDD) + (ISS × VSS).
9
All dynamic characteristics use VDD = +2.5 V and VSS = −2.5 V.
Rev. B | Page 4 of 28
AD5235
INTERFACE TIMING AND EEMEM RELIABILITY CHARACTERISTICS—25 KΩ, 250 KΩ VERSIONS
Guaranteed by design and not subject to production test.
See the Timing Diagrams section for the location of measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to
90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using both VDD = 3 V and 5 V.
Table 2.
Parameter
Clock Cycle Time (tCYC)
CS Setup Time
CLK Shutdown Time to CS Rise
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CS to SDO-SPI Line Acquire
CS to SDO-SPI Line Release
CLK to SDO Propagation Delay2
CLK to SDO Data Hold Time
CS High Pulse Width3
CS High to CS High3
RDY Rise to CS Fall
CS Rise to RDY Fall Time
Store/Read EEMEM Time4
CS Rise to Clock Rise/Fall Setup
Preset Pulse Width (Asynchronous)
Preset Response Time to Wiper Setting
Power-On EEMEM Restore Time
FLASH/EE MEMORY RELIABILITY
Endurance5
Data Retention6
Symbol
t1
t2
t3
t4, t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
tPRW
tPRESP
tEEMEM1
Conditions
Clock level high or low
From positive CLK transition
From positive CLK transition
RP = 2.2 kΩ, CL < 20 pF
RP = 2.2 kΩ, CL < 20 pF
Min
20
10
1
10
5
5
Typ1
Max
140
140
Unit
ns
ns
tCYC
ns
ns
ns
ns
ns
ns
ns
ns
tCYC
ns
ms
ms
ns
ns
µs
µs
100
kCycles
Years
40
50
50
0
10
4
0
0.15
30
Applies to instructions 0x2, 0x3, and 0x9
10
50
0.3
www.BDTIC.com/ADI
Not shown in timing diagram
PR pulsed low to refresh wiper positions
100
1
Typicals represent average readings at 25°C and VDD = 5 V.
Propagation delay depends on the value of VDD, RPULL-UP, and CL.
3
Valid for commands that do not activate the RDY pin.
4
RDY pin low only for Instructions 2, 3, 8, 9, 10, and the PR hardware pulse: CMD_8 ~ 1 ms; CMD_9, 10 ~ 0.1 ms; CMD_2, 3 ~ 20 ms. Device operation at TA = −40°C and
VDD < 3 V extends the save time to 35 ms.
5
Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.
6
Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV
derates with junction temperature in the Flash/EE memory.
2
Rev. B | Page 5 of 28
AD5235
TIMING DIAGRAMS
CPHA = 1
CS
t12
t13
t3
t1
t2
CLK
CPOL = 1
t5
B23
B0
t17
t4
t7
t6
HIGH
OR LOW
SDI
B23–MSB
t8
t11
t10
B24*
SDO
HIGH
OR LOW
B0–LSB
t9
B23–MSB
B0–LSB
t14
t15
02816-B-002
t16
RDY
*NOTE: EXTRA BIT THAT IS NOT DEFINED, BUT NORMALLY LSB OF CHARACTER PREVIOUSLY TRANSMITTED.
THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
www.BDTIC.com/ADI
Figure 2. CPHA = 1 Timing Diagram
CPHA = 0
CS
t12
t1
t3
t2
t5
B23
CLK
CPOL = 0
t13
t17
B0
t4
t7
t6
SDI
HIGH
OR LOW
t8
HIGH
OR LOW
B0–LSB
B23–MSB IN
t10
t11
t9
SDO
B23–MSB OUT
B0–LSB
t14
*
t15
*NOTE: EXTRA BIT THAT IS NOT DEFINED, BUT NORMALLY MSB OF CHARACTER JUST RECEIVED.
THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
Figure 3. CPHA = 0 Timing Diagram
Rev. B | Page 6 of 28
02816-B-003
t16
RDY
AD5235
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to GND
VSS to GND
VDD to VSS
VA, VB, VW to GND
IA, IB, IW
Pulsed1
Continuous
Digital Input and Output Voltage to GND
Operating Temperature Range2
Maximum Junction Temperature (TJ max)
Storage Temperature
Lead Temperature, Soldering
Vapor Phase (60 s)
Infrared (15 s)
Thermal Resistance Junction-to-Ambient
θJA,TSSOP-16
Thermal Resistance Junction-to-Case θJC,
TSSOP-16
Package Power Dissipation
1
Rating
–0.3 V, +7 V
+0.3 V, −7 V
7V
VSS − 0.3 V, VDD + 0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
±20 mA
±2 mA
−0.3 V, VDD + 0.3 V
−40°C to +85°C
150°C
−65°C to +150°C
215°C
220°C
150°C/W
28°C/W
(TJ max − TA)/θJA
www.BDTIC.com/ADI
Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2
Includes programming of nonvolatile memory.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 7 of 28
AD5235
CLK 1
16
RDY
SDI 2
15
CS
SDO 3
14
PR
13
WP
12
VDD
11
A2
W1 7
10
W2
B1 8
9
B2
GND 4
VSS 5
A1 6
AD5235BRU
TOP VIEW
(Not to Scale)
02816-B-005
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
Mnemonic
CLK
SDI
SDO
4
5
GND
VSS
6
7
8
9
10
11
12
13
A1
W1
B1
B2
W2
A2
VDD
WP
14
PR
15
16
CS
RDY
Description
Serial Input Register Clock. Shifts in one bit at a time on positive clock edges.
Serial Data Input. Shifts in one bit at a time on positive clock CLK edges. MSB loads first.
Serial Data Output. Serves readback and daisy-chain functions.
Commands 9 and 10 activate the SDO output for the readback function, delayed by 24 or 25 clock pulses,
depending on the clock polarity before and after the data-word (see Figure 2, Figure 3, and Table 7).
In other commands, the SDO shifts out the previously loaded SDI bit pattern, delayed by 24 or 25 clock pulses
depending on the clock polarity (see Figure 2 and Figure 3). This previously shifted-out SDI can be used for daisychaining multiple devices.
Whenever SDO is used, a pull-up resistor in the range of 1 kΩ to 10 kΩ is needed.
Ground Pin, Logic Ground Reference.
Negative Supply. Connect to 0 V for single-supply applications. If VSS is used in dual supply, it must be able to sink
35 mA for 30 ms when storing data to EEMEM.
Terminal A of RDAC1.
Wiper terminal of RDAC1. ADDR(RDAC1) = 0x0.
Terminal B of RDAC1.
Terminal B of RDAC2.
Wiper terminal of RDAC2. ADDR(RDAC2) = 0x1.
Terminal A of RDAC2.
Positive Power Supply.
Optional Write Protect. When active low, WP prevents any changes to the present contents, except PR strobe.
CMD_1 and COMD_8 refresh the RDAC register from EEMEM. Execute a NOP instruction before returning to WP
high. Tie WP to VDD, if not used.
Optional Hardware Override Preset. Refreshes the scratchpad register with current contents of the EEMEM
register. Factory default loads midscale 51210 until EEMEM is loaded with a new value by the user. PR is activated
at the logic high transition. Tie PR to VDD, if not used.
Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high.
Ready. Active-high open-drain output. Identifies completion of Instructions 2, 3, 8, 9, 10, and PR.
www.BDTIC.com/ADI
Rev. B | Page 8 of 28
AD5235
TYPICAL PERFORMANCE CHARACTERISTICS
0.4
1.0
+25°C
–40°C
+85°C
0.8
+25°C
–40°C
+85°C
0.2
R-DNL ERROR (LSB)
0.6
INL ERROR (LSB)
0.4
0.2
0.0
–0.2
0.0
–0.2
–0.4
–0.4
–0.6
–0.6
0
200
400
600
800
–0.8
02816-B-006
–1.0
1000
DIGITAL CODE
0
200
400
600
800
1000
DIGITAL CODE
Figure 5. INL vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 25 kΩ
02816-B-009
–0.8
Figure 8. R-DNL vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 25 kΩ
1.0
+25°C
–40°C
+85°C
70
POTENTIOMETER MODE TEMPCO (ppm/°C)
0.8
0.6
0.2
0.0
50
25kΩ VERSION
40
250kΩ VERSION
www.BDTIC.com/ADI
–0.4
–0.6
–0.8
–1.0
–1.2
0
200
400
600
800
02816-B-007
–1.4
1000
DIGITAL CODE
20
10
0
–10
–20
–30
0
128
256
384
512
640
768
896
1023
CODE (Decimal)
Figure 6. DNL vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 25 kΩ
Figure 9. (∆VW/VW)/∆T × 106 Potentiometer Mode Tempco
1.0
120
+25°C
–40°C
+85°C
0.6
0.4
0.2
0
–0.2
–0.4
80
60
40
20
0
–20
25kΩ VERSION
–40
250kΩ VERSION
–60
–0.6
0
200
400
600
800
02816-B-008
R-INL ERROR (LSB)
VDD/VSS = 5V/0V
TA = 25°C
100
RHEOSTAT MODE TEMPCO (ppm/°C)
0.8
02816-B-010
–0.2
30
1000
DIGITAL CODE
Figure 7. R-INL vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 25 kΩ
Rev. B | Page 9 of 28
–80
0
128
256
384
512
640
768
896
1023
CODE (Decimal)
Figure 10. (∆RWB/RWB)/∆T × 106 Rheostat Mode Tempco
02816-B-011
DNL ERROR (LSB)
0.4
VDD/VSS = 5V/0V
TA = 25°C
60
AD5235
36
0.28
VDD = 3V
VSS = 0V
TA = 25°C
34
32
0.20
THD + NOISE (%)
30
28
Ω
VDD/VSS = ±2.5V
VA = 1V rms
0.24
26
24
22
RAB = 250kΩ
0.16
0.12
25kΩ
0.08
20
0.04
0
200
400
600
800
1000
1200
CODE (Decimal)
0.00
0.01k
02816-B-012
16
0.1k
1k
10k
Figure 11. Wiper On Resistance vs. Code
Figure 14. Total Harmonic Distortion vs. Frequency
4
3
3
0
RAB = 25kΩ
2
GAIN (dB)
1
–3
RAB = 250kΩ
–6
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ISS @ VDD/VSS = 5V/0V
–9
IDD @ VDD/VSS = 2.7V/0V
ISS @ VDD/VSS = 2.7V/0V
–20
0
20
40
60
80
100
CODE (Decimal)
VDD/VSS = ±2.5V
VA = 1V rms
D = MIDSCALE
–12
1k
02816-B-013
–1
–40
f–3dB = 125kHz
10k
100k
1M
FREQUENCY (Hz)
Figure 12. IDD vs. Temperature, RAB = 25 kΩ
02816-B-016
0
f–3dB = 12kHz
Figure 15. −3 dB Bandwidth vs. Resistance ( Figure 31)
0.25
0
VDD/VSS = 5V/0V
RAR = 25kΩ
CODE 0x200
FULL SCALE
–10
0.20
0x100
0x080
MIDSCALE
–20
GAIN (dB)
0.15
ZERO SCALE
0.10
0x040
0x020
–30
0x010
0x008
–40
0x004
0x002
0.05
–50
0.00
0
2M
4M
6M
8M
10M
FREQUENCY (Hz)
12M
02816-B-014
0x001
Figure 13. IDD vs. Clock Frequency, RAB = 25 kΩ
–60
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 16. Gain vs. Frequency vs. Code, RAB = 25 kΩ ( Figure 31)
Rev. B | Page 10 of 28
02816-B-017
CURRENT ( µA)
IDD @ VDD/VSS = 5V/0V
I DD (mA)
100k
FREQUENCY (Hz)
02816-B-015
18
AD5235
0
2.64
CODE 0x200
0x100
2.60
0x080
2.58
0x040
2.56
0x020
–30
0x010
0x008
–40
–50
2.54
2.52
2.50
0x004
2.48
0x002
2.46
0x001
2.44
1k
10k
100k
2.42
02816-B-018
–60
1M
FREQUENCY (Hz)
0
10
20
30
40
02816-B-021
GAIN (dB)
–20
VDD = VSS = 5V
CODE = 0x200 TO 0x1FF
2.62
AMPLITUDE (V)
–10
50
TIME (µS)
Figure 17. Gain vs. Frequency vs. Code, RAB = 250 kΩ ( Figure 31)
Figure 20. Midscale Glitch Energy, RAB = 25 kΩ, Code 0x200 to 0x1FF
80
2.65
70
2.60
60
40
2.55
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2.45
VDD = 5V ± 100mV AC
VSS = 0V, VA = 5V, VB = 0V
MEASURED AT VW WITH CODE = 0x200
TA = 25°C
0.1k
1k
10k
100k
1M
10M
FREQUENCY (Hz)
0
10
20
30
40
50
TIME (µS)
Figure 21. Midscale Glitch Energy, RAB = 250 kΩ, Code 0x200 to 0x1FF
Figure 18. PSRR vs. Frequency
VDD = 5V
VA = 2.25V
VB = 0
TA = 25°C
0.5V/DIV
2.40
02816-B-019
0
0.01k
02816-B-022
20
2.50
VA
0.5V/DIV
5V/DIV
CS
5V/DIV
CLK
5V/DIV
SDI
VW(D)
0.5/DIV
MIDSCALE
IDD
20mA/DIV
50µS/DIV
4ms/DIV
Figure 19. Power-On Reset, VDD = 2.25 V,
Previously Stored Code = 0x2AA
Figure 22. IDD vs. Time when Storing Data to EEMEM
Rev. B | Page 11 of 28
02816-B-023
30
10
AMPLITUDE (V)
RAB = 250kΩ
02816-B-020
PSRR ( –dB)
RAB = 25kΩ
50
AD5235
100
VA = VB = OPEN
TA = 25°C
5V/DIV
CLK
5V/DIV
SDI
5V/DIV
IDD*
2mA/DIV
THEORECTICAL (IWB_MAX – mA)
CS
10
1
RAB = 25kΩ
0.1
RAB = 250kΩ
0.01
0
128
256
384
512
640
768
02816-B-025
02816-B-024
4ms/DIV
* SUPPLY CURRENT RETURNS TO MINIMUM POWER
CONSUMPTION, IF INSTRUCTION 0 (NOP) IS EXECUTED
IIMMEDIATELY AFTER INSTRUCTION 1 (READ EEMEM).
1024
896
CODE (Decimal)
Figure 23. IDD vs. Time when Restoring Data from EEMEM
Figure 24. IWB_MAX vs. Code
TEST CIRCUITS
Figure 25 to Figure 35 define the test conditions used in the Specifications section.
NC
DUT
A
W
VA
IW
V+ = VDD ±10%
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B
V+
NC = NO CONNECT
~
Figure 25. Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
W
PSS (%/%) =
VMS
V+ = V DD
1LSB = V+/2N
A
∆VDD
∆VDD%
DUT B
5V
VMS
W
VIN
02816-B-027
B
∆VMS
Figure 28. Power Supply Sensitivity
(PSS, PSRR)
W
V+
∆VMS%
(
OP279
OFFSET
GND
VOUT
02816-B-030
DUT
A
PSRR (dB) = 20 LOG
B
02816-B-026
VMS
A
OFFSET BIAS
Figure 26. Potentiometer Divider Nonlinearity Error
(INL, DNL)
Figure 29. Inverting Gain
5V
IW = VDD/RNOMINAL
DUT
W
VW
OP279
VMS1
RW = [VMS1 – VMS2 ] / IW
02816-B-028
VIN
B
VOUT
W
OFFSET
GND
A
DUT
B
OFFSET BIAS
Figure 27. Wiper Resistance
Figure 30. Noninverting Gain
Rev. B | Page 12 of 28
02816-B-031
A
VMS2
)
02816-B-029
VDD
AD5235
+15V
DUT
OP42
B
OFFSET
GND
2.5V
–15V
NC
A2
RDAC2
W2
W1
B1
Figure 31. Gain vs. Frequency
VOUT
B2
VSS
CTA = 20 LOG [VOUT/VIN]
NC = NO CONNECT
Figure 34. Analog Crosstalk
0.1V
ISW
CODE = 0x00
RSW =
DUT
RDAC1
VIN
VOUT
02816-B-032
VIN
VDD
A1
W
02816-B-035
A
200µA
W
IOL
+
0.1V
ISW
–
VOH (MIN)
OR
VOL (MAX)
CL
50pF
200µA
IOH
Figure 32. Incremental On Resistance
Figure 35. Load Circuit for Measuring VOH and VOL (The diode bridge test
circuit is equivalent to the application circuit with RPULL-UP of 2.2 kΩ.)
NC
VDD
DUT
A
VSS GND
B
02816-B-036
VSS TO VDD
A = NC
TO OUTPUT
PIN
02816-B-033
B
ICM
W
NC
NC = NO CONNECT
02816-B-034
VCM
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Figure 33. Common-Mode Leakage Current
Rev. B | Page 13 of 28
AD5235
THEORY OF OPERATION
The AD5235 digital potentiometer is designed to operate as a
true variable resistor. The resistor wiper position is determined
by the RDAC register contents. The RDAC register acts as a
scratchpad register, allowing unlimited changes of resistance
settings. The scratchpad register can be programmed with any
position setting using the standard SPI serial interface by
loading the 24-bit data-word. In the format of the data-word,
the first four bits are commands, the following four bits are
addresses, and the last 16 bits are data. Once a specified value is
set, this value can be stored in a corresponding EEMEM
register. During subsequent power-up, the wiper setting is
automatically loaded to that value.
Storing data to EEMEM takes about 25 ms and consumes
approximately 35 mA. During this time, the shift register is
locked, preventing any changes from taking place. The RDY pin
pulses low to indicate the completion of this EEMEM storage.
There are also 13 addresses with two bytes each of user-defined
data that can be stored in EEMEM.
SCRATCHPAD AND EEMEM PROGRAMMING
The scratchpad RDAC register directly controls the position of
the digital potentiometer wiper. For example, when the scratchpad register is loaded with all zeros, the wiper is connected to
Terminal B of the variable resistor. The scratchpad register is a
standard logic register with no restriction on the number of
changes allowed, but the EEMEM registers have a program
erase/write cycle limitation.
BASIC OPERATION
The basic mode of setting the variable resistor wiper position
(programming the scratchpad register) is accomplished by
loading the serial data input register with Instruction 11 (0xB),
Address 0, and the desired wiper position data. When the
proper wiper position is determined, the user can load the serial
data input register with Instruction 2 (0x2), which stores the
wiper position data in the EEMEM register. After 25 ms, the
wiper position is permanently stored in nonvolatile memory.
Table 5 provides a programming example listing the sequence
of serial data input (SDI) words with the serial data output
appearing at the SDO pin in hexadecimal format.
The following instructions facilitate the user’s programming
needs (see Table 7 for details):
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0.
Do nothing.
1.
Restore EEMEM content to RDAC.
2.
Store RDAC setting to EEMEM.
3.
Store RDAC setting or user data to EEMEM.
4.
Decrement 6 dB.
5.
Decrement all 6 dB.
6.
Decrement one step.
7.
Decrement all one step.
8.
Reset EEMEM content to RDAC.
9.
Read EEMEM content from SDO.
Table 5. Write and Store RDAC Settings to EEMEM
Registers
SDI
0xB00100
SDO
0xXXXXXX
0x20XXXX
0xB00100
0xB10200
0x20XXXX
0x21XXXX
0xB10200
Action
Writes data 0x100 to the RDAC1
register, Wiper W1 moves to 1/4 fullscale position.
Stores RDAC1 register content into
the EEMEM1 register.
Writes 0x200 data into the RDAC2
register, Wiper W2 moves to 1/2 fullscale position.
Stores RDAC2 register contents into
EEMEM2 register.
At system power-on, the scratchpad register is automatically
refreshed with the value previously stored in the corresponding
EEMEM register. The factory-preset EEMEM value is midscale.
The scratchpad register can also be refreshed with the contents
of the EEMEM register in three different ways. First, executing
Instruction 1 (0x1) restores the corresponding EEMEM value.
Second, executing Instruction 8 (0x8) resets both channels’
EEMEM values. Finally, pulsing the PR pin refreshes both
EEMEM settings. Operating the hardware control PR function
requires a complete pulse signal. When PR goes low, the internal
logic sets the wiper at midscale. The EEMEM value is not
loaded until PR returns high.
10. Read RDAC wiper setting from SDO.
11. Write data to RDAC.
12. Increment 6 dB.
13. Increment all 6 dB.
14. Increment one step.
15. Increment all one step.
Table 14 to Table 20 provide programming examples that use
some of these commands.
Rev. B | Page 14 of 28
AD5235
VDD
EEMEM PROTECTION
The write protect (WP) pin disables any changes to the
scratchpad register contents, except for the EEMEM setting,
which can still be restored using Instruction 1, Instruction 8,
and the PR pulse. Therefore, WP can be used to provide a
hardware EEMEM protection feature. To disable WP, it is
recommended to execute a NOP instruction before returning
WP to logic high.
INPUT
300Ω
GND
DIGITAL INPUT/OUTPUT CONFIGURATION
02816-B-039
WP
Figure 38. Equivalent WP Input Protection
All digital inputs are ESD protected, high input impedance that
can be driven directly from most digital sources. Active at logic
low, PR and WP must be tied to VDD, if they are not used. No
internal pull-up resistors are present on any digital input pins.
To avoid floating digital pins that might cause false triggering in
a noisy environment, pull-up resistors should be added. This is
applicable when the device is detached from the driving source
once it is programmed.
The SDO and RDY pins are open-drain digital outputs that
need pull-up resistors only if these functions are used. To
optimize the speed and power trade-off, use 2.2 kΩ pull-up
resistors.
SERIAL DATA INTERFACE
The AD5235 contains a 4-wire SPI compatible digital interface
(SDI, SDO, CS, and CLK). The 24-bit serial data-word must be
loaded with MSB first. The format of the word is shown in
Table 6. The command bits (C0 to C3) control the operation of
the digital potentiometer according to the command shown in
Table 7. A0 to A3 are the address bits. A0 is used to address
RDAC1 or RDAC2. Addresses 2 to 14 are accessible by users for
extra EEMEM. Address 15 is reserved for factory usage. Table 9
provides an address map of the EEMEM locations. The data bits
(D0 to D9) are the values for the RDAC registers. The data bits
(D0 to D15) are the values for the EEMEM registers.
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The equivalent serial data input and output logic is shown in
Figure 36. The open-drain output SDO is disabled whenever
chip-select CS is in logic high. ESD protection of the digital
inputs is shown in Figure 37 and Figure 38.
PR
VALID
COMMAND
COUNTER
WP
COMMAND
PROCESSOR
AND ADDRESS
DECODE
5V
RPULL-UP
CLK
SERIAL
REGISTER
(FOR DAISY
CHAIN ONLY)
GND
AD5235
SDI
Figure 36. Equivalent Digital Input-Output Logic
VDD
INPUTS
300Ω
GND
The SPI interface can be used in two slave modes: CPHA = 1,
CPOL = 1 and CPHA = 0, CPOL = 0. CPHA and CPOL refer to
the control bits that dictate SPI timing in the following
MicroConverters and microprocessors: ADuC812/ADuC824,
M68HC11, and MC68HC16R1/MC68HC 916R1.
DAISY-CHAIN OPERATION
02816-B-038
LOGIC
PINS
02816-B-037
SDO
CS
The AD5235 has an internal counter that counts a multiple of
24 bits (a frame) for proper operation. For example, AD5235
works with a 24-bit or 48-bit word, but it cannot work properly
with a 23-bit or 25-bit word. In addition, AD5235 has a subtle
feature that, if CS is pulsed without CLK and SDI, the part
repeats the previous command (except during power-up). As a
result, care must be taken to ensure that no excessive noise
exists in the CLK or CS line that might alter the effective
number-of-bits pattern. Also, to prevent data from mislocking
(due to noise, for example), the counter resets, if the count is not
a multiple of four when CS goes high.
Figure 37. Equivalent ESD Digital Input Protection
The serial data output pin (SDO) serves two purposes. It can be
used to read the contents of the wiper setting and EEMEM
values using Instructions 10 and 9, respectively. The remaining
instructions (0 to 8, 11 to 15) are valid for daisy-chaining
multiple devices in simultaneous operations. Daisy-chaining
minimizes the number of port pins required from the
controlling IC (Figure 39). The SDO pin contains an open-drain
N-Ch FET that requires a pull-up resistor, if this function is
used. As shown in Figure 39, users need to tie the SDO pin of
one package to the SDI pin of the next package. Users might
need to increase the clock period, because the pull-up resistor
Rev. B | Page 15 of 28
AD5235
and the capacitive loading at the SDO–SDI interface might
require additional time delay between subsequent devices.
the common-mode voltage range of the three terminals extends
from VSS to VDD, regardless of the digital input level.
When two AD5235s are daisy-chained, 48 bits of data are
required. The first 24 bits (formatted 4-bit command, 4-bit
address, and 16-bit data) go to U2, and the second 24 bits with
the same format go to U1. The CS should be kept low until all
48 bits are clocked into their respective serial registers. The CS
is then pulled high to complete the operation.
Power-Up Sequence
VDD
AD5235
MOSI
µC
SDI
U1
SDO
RP
2.2kΩ
AD5235
SDI
U2 SDO
SCLK SS
CLK
CLK
CS
02816-B-040
CS
Because there are diodes to limit the voltage compliance at
Terminals A, B, and W (Figure 40), it is important to power
VDD/VSS first before applying any voltage to Terminals A, B,
and W. Otherwise, the diode is forward-biased such that VDD/VSS
are powered unintentionally. For example, applying 5 V across
Terminals A and B prior to VDD causes the VDD terminal to
exhibit 4.3 V. It is not destructive to the device, but it might
affect the rest of the user’s system. The ideal power-up sequence
is GND, VDD/VSS, digital inputs, and VA, VB, and VW. The order
of powering VA, VB, VW, and digital inputs is not important as
long as they are powered after VDD/VSS.
Figure 39. Daisy-Chain Configuration Using SDO
Regardless of the power-up sequence and the ramp rates of the
power supplies, once VDD/VSS are powered, the power-on preset
activates, which restores the EEMEM values to the RDAC
registers.
TERMINAL VOLTAGE OPERATING RANGE
Layout and Power Supply Bypassing
The AD5235’s positive VDD and negative VSS power supplies
define the boundary conditions for proper 3-terminal digital
potentiometer operation. Supply signals present on Terminals A,
B, and W that exceed VDD or VSS are clamped by the internal
forward-biased diodes (see Figure 40).
It is a good practice to employ compact, minimum lead-length
layout design. The leads to the input should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
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Similarly, it is good practice to bypass the power supplies with
quality capacitors for optimum stability. Supply leads to the
device should be bypassed with 0.01 µF to 0.1 µF disk or chip
ceramic capacitors. Low ESR, 1 µF to 10 µF tantalum or
electrolytic capacitors should also be applied at the supplies to
minimize any transient disturbance (see Figure 41).
VDD
A
W
B
VSS
Figure 40. Maximum Terminal Voltages Set by VDD and V SS
C3
10µF
+
C1
0.1µF
C4
10µF
+
C2
0.1µF
VDD
VSS
GND
The ground pin of the AD5235 device is primarily used as a
digital ground reference. To minimize the digital ground
bounce, the AD5235 ground terminal should be joined remotely
to the common ground (see Figure 41). The digital input
control signals to the AD5235 must be referenced to the device
ground pin (GND), and satisfy the logic level defined in the
Specifications section. An internal level-shift circuit ensures that
Rev. B | Page 16 of 28
Figure 41. Power Supply Bypassing
02816-B-042
VDD
02816-B-041
VSS
AD5235
AD5235
In Table 6, command bits are C0 to C3, address bits are A0 to A3, data bits D0 to D9 are applicable to RDAC, and D0 to D15 are applicable
to EEMEM.
Table 6. 24-Bit Serial Data-Word
MSB
RDAC
EEMEM
C3
C3
Command Byte 0
C2
C2
C1
C1
C0
C0
0
A3
Data Byte 1
0
A2
0
A1
A0
A0
X
D15
X
D14
Data Byte 0
X
D13
X
D12
X
D11
X
D10
D9
D9
D8
D8
Data Byte 1
B15
X
… D9
X
… X
X
… X
B8
D8
X
X
Data Byte 0
B7
B0
D7 … D0
X
… X
X
… X
X
X
…
X
D8
D7
…
D0
X
X
…
X
D7
D7
D6
D6
D5
D5
LSB
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Command instruction codes are defined in Table 7.
Table 7. Command Operation Truth Table1, 2, 3
0
1
Command Byte 0
B23
C3
C2 C1 C0
0
0
0
0
0
0
0
1
A3
X
0
A2
X
0
A1
X
0
B16
A0
X
A0
2
0
0
1
0
0
0
0
A0
X
…
34
0
0
1
1
A3
A2
A1
A0
D15
…
45
0
1
0
0
0
0
0
A0
X
…
Command
Number
55
X
X
1
0
1
X
X
X
X
X
…
X
X
X
…
X
0
1
1
0
0
0
0
A0
X
…
X
X
X
…
X
0
1
1
1
X
X
X
X
X
…
X
X
X
…
X
8
1
0
0
0
0
0
0
0
X
…
X
X
X
…
X
9
1
0
0
1
A3
A2
A1
A0
X
…
X
X
X
…
X
10
1
0
1
0
0
0
0
A0
X
…
X
X
X
…
X
11
1
0
1
1
0
0
0
A0
X
…
D9
D8
D7
…
D0
125
1
1
0
0
0
0
0
A0
X
…
X
X
X
…
X
135
1
1
0
1
X
X
X
X
X
…
X
X
X
…
X
145
1
1
1
0
0
0
0
A0
X
…
X
X
X
…
X
155
1
1
1
1
X
X
X
X
X
…
X
X
X
…
X
75
NOP: Do nothing. See Table 16.
Restore EEMEM(A0) contents to RDAC(A0)
register. This command leaves the device in the
read program power state. To return the part to
the idle state, perform NOP instruction 0. See
Table 16.
Store Wiper Setting: Store RDAC(A0) setting to
EEMEM(A0). See Table 15.
Store contents of Serial Register Data Bytes 0
and 1 (total 16 bits) to EEMEM(ADDR). See
Table 18.
Decrement 6 dB: Right-shift contents of
RDAC(A0) register, stop at all 0s.
Decrement all 6 dB: Right-shift contents of all
RDAC registers, stop at all 0s.
Decrement contents of RDAC(A0) by 1, stop at
all 0s.
Decrement contents of all RDAC registers by 1,
stop at all 0s.
Reset: Refresh all RDACs with their corresponding EEMEM previously stored values.
Read contents of EEMEM (ADDR) from SDO
output in the next frame. See Table 19.
Read RDAC wiper setting from SDO output in
the next frame. See Table 20.
Write contents of Serial Register Data Bytes 0
and 1 (total 10 bits) to RDAC(A0). See Table 14.
Increment 6 dB: Left-shift contents of
RDAC(A0), stop at all 1s. See Table 17.
Increment all 6 dB: Left-shift contents of all
RDAC registers, stop at all 1s.
Increment contents of RDAC(A0) by 1, stop at
all 1s. See Table 15.
Increment contents of all RDAC registers by 1,
stop at all 1s.
www.BDTIC.com/ADI
0
65
Operation
1
The SDO output shifts out the last 24 bits of data clocked into the serial register for daisy-chain operation. Exception: for any instruction following Instruction 9 or 10,
the selected internal register data is present in Data Bytes 0 and 1. The instructions following Instructions 9 and 10 must also be a full 24-bit data-word to completely
clock out the contents of the serial register.
2
The RDAC register is a volatile scratchpad register that is refreshed at power-on from the corresponding nonvolatile EEMEM register.
3
Execution of these operations takes place when the CS strobe returns to logic high.
4
Instruction 3 writes two data bytes (16 bits of data) to EEMEM. In the case of Addresses 0 and 1, only the last 10 bits are valid for wiper position setting.
5
The increment, decrement, and shift instructions ignore the contents of the shift register Data Bytes 0 and 1.
Rev. B | Page 17 of 28
AD5235
data in the RDAC register is automatically set to full scale. This
makes the left-shift function as ideal a logarithmic adjustment
as possible.
ADVANCED CONTROL MODES
The AD5235 digital potentiometer includes a set of user
programming features to address the wide number of
applications for these universal adjustment devices.
Key programming features include:
• Scratchpad programming to any desirable values
• Nonvolatile memory storage of the scratchpad RDAC register
value in the EEMEM register
• Increment and decrement instructions for the RDAC wiper
register
The right-shift 4 and 5 instructions are ideal only if the LSB is 0
(ideal logarithmic = no error). If the LSB is a 1, the right-shift
function generates a linear half-LSB error, which translates to a
number-of-bits dependent logarithmic error, as shown in Figure
42. The plot shows the error of the odd numbers of bits for the
AD5235.
Table 8. Detail Left-Shift and Right-Shift Functions for 6 dB
Step Increment and Decrement
Left-Shift
00 0000 0000
00 0000 0001
00 0000 0010
00 0000 0100
00 0000 1000
00 0001 0000
00 0010 0000
00 0100 0000
00 1000 0000
01 0000 0000
10 0000 0000
11 1111 1111
11 1111 1111
• Left and right bit shift of the RDAC wiper register to achieve
±6 dB level changes
• 26 extra bytes of user-addressable nonvolatile memory
Linear Increment and Decrement Instructions
The increment and decrement instructions (14, 15, 6, and 7) are
useful for linear step-adjustment applications. These commands
simplify microcontroller software coding by allowing the
controller to send just an increment or decrement command to
the device. The adjustment can be individual or ganged control.
Left-Shift
(+6 dB/Step)
Right-Shift
11 1111 1111
01 1111 1111
00 1111 1111
00 0111 1111
00 0011 1111
00 0001 1111
00 0000 1111
00 0000 0111
00 0000 0011
00 0000 0001
00 0000 0000
00 0000 0000
00 0000 0000
Right-Shift
(–6 dB/Step)
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Four programming instructions produce logarithmic taper
increment and decrement of the wiper position control by
either individual or ganged control. The 6 dB increment is
activated by Instructions 12 and 13, and the 6 dB decrement is
activated by Instructions 4 and 5. For example, executing the
increment Instruction 12 eleven times moves the wiper in 6 dB
per step from 0% to full scale, RAB. When the wiper position is
near the maximum setting, the last 6 dB increment instruction
causes the wiper to go to the full-scale 1023 code position.
Further 6 dB per increment instructions do not change the
wiper position beyond its full scale (see Table 8).
The 6 dB step increments and 6 dB step decrements are
achieved by shifting the bit internally to the left or right,
respectively. The following information explains the nonideal
±6 dB step adjustment under certain conditions. Table 8
illustrates the operation of the shifting function on the RDAC
register data bits. Each table row represents a successive shift
operation. Note that the left-shift 12 and 13 instructions were
modified such that, if the data in the RDAC register is equal to
zero and the data is shifted left, the RDAC register is then set to
Code 1. Similarly, if the data in the RDAC register is greater
than or equal to midscale and the data is shifted left, then the
0
–20
–40
–60
–80
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
CODE (From 1 to 1023 by 2.0 × 103)
0.9
1.0
1.1
02816-B-043
Logarithmic Taper Mode Adjustment
Actual conformance to a logarithmic curve between the data
contents in the RDAC register and the wiper position for each
right-shift 4 and 5 command execution contains an error only
for odd numbers of bits. Even numbers of bits are ideal. The
graph in Figure 42 shows plots of Log_Error [20 × log10
(error/code)] for the AD5235. For example, Code 3 Log_Error =
20 × log10 (0.5/3) = −15.56 dB, which is the worst case. The plot
of Log_Error is more significant at the lower codes.
dB
For an increment command, executing Instruction 14 automatically moves the wiper to the next resistance segment position.
The master increment command, Instruction 15, moves all
resistor wipers up by one position.
Figure 42. Plot of Log_Error Conformance for Odd Numbers of Bits Only
(Even Numbers of Bits Are Ideal)
Rev. B | Page 18 of 28
AD5235
Using CS to Re-Execute a Previous Command
calculated as follows:
Another subtle feature of the AD5235 is that a subsequent CS
strobe, without clock and data, repeats a previous command.
MSB: 1 = Positive
Next 7 LSB: 001 1100 = 28
8 LSB: 0000 1111 = 15 × 2−8 = 0.06
% Tolerance = 28.06%
Therefore, RAB_ACTUAL = 320.15 kΩ
Using Additional Internal Nonvolatile EEMEM
The AD5235 contains additional user EEMEM registers for
storing any 16-bit data such as memory data for other components, look-up tables, or system identification information.
Table 9 provides an address map of the internal storage registers
shown in the functional block diagram as EEMEM1, EEMEM2,
and 26 bytes (13 addresses × 2 bytes each) of USER EEMEM.
RDAC STRUCTURE
The patent-pending RDAC contains multiple strings of equal
resistor segments with an array of analog switches that acts as
the wiper connection. The number of positions is the resolution
of the device. The AD5235 has 1024 connection points, allowing
it to provide better than 0.1% settability resolution. Figure 43
shows an equivalent structure of the connections among the
three terminals of the RDAC. The SWA and SWB are always on,
while the switches SW(0) to SW(2N−1) are on one at a time,
depending on the resistance position decoded from the data
bits. Because the switch is not ideal, there is a 50 Ω wiper
resistance, RW. Wiper resistance is a function of supply voltage
and temperature. The lower the supply voltage or the higher the
temperature, the higher the resulting wiper resistance. Users
should be aware of the wiper resistance dynamics, if accurate
prediction of the output resistance is needed.
Table 9. EEMEM Address Map
EEMEM No.
1
2
3
4
…
15
16
Address
0000
0001
0010
0011
…
1110
1111
EEMEM Content for …
RDAC11, 2
RDAC2
USER13
USER2
…
USER13
RAB1 Tolerance4
1
RDAC data stored in EEMEM locations is transferred to the corresponding
RDAC register at power-on, or when Instruction 1, Instruction 8, and PR are
executed.
2
Execution of Instruction 1 leaves the device in the read mode power
consumption state. After the last Instruction 1 is executed, the user should
perform a NOP, Instruction 0, to return the device to the low power idling
state.
3
USERx are internal nonvolatile EEMEM registers available to store and
retrieve constants and other 16-bit information using Instruction 3 and
Instruction 9, respectively.
4
Read only.
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SWA
A
SW(2N–1)
RDAC
WIPER
REGISTER
AND
DECODER
Calculating Actual End-to-End Terminal Resistance
The resistance tolerance is stored in the EEMEM register during
factory testing. The actual end-to-end resistance can, therefore,
be calculated, which is valuable for calibration, tolerance
matching, and precision applications. Note that this value is
read only and the RAB2 matches with RAB1, typically 0.1%.
RS
W
SW(2N–2)
RS
SW(1)
RS
SW(0)
DIGITAL
CIRCUITRY
OMITTED FOR
CLARITY
The resistance tolerance in percentage is contained in the last
16 bits of data in EEMEM Register 15. The format is the sign
magnitude binary format with the MSB designate for sign (0 =
negative and 1 = positive), the next 7 MSB designate the integer
number, and the 8 LSB designate the decimal number (see
Table 11).
SWB
B
02816-B-044
RS = RAB/2N
Figure 43. Equivalent RDAC Structure
Table 10. Nominal Individual Segment Resistor Values
Device Resolution
1024-Step
For example, if RAB_RATED = 250 kΩ and the data in the SDO
shows XXXX XXXX 1001 1100 0000 1111, RAB_ACTUAL can be
25 kΩ
24.4
250 kΩ
244
Table 11. Calculating End-to-End Terminal Resistance
Bit
Sign
Mag
D15
D14
D13
Sign
26
25
D12
D11
D10
D9
24
23
22
21
7 Bits for Integer Number
D8
20
.
Decimal
Point
Rev. B | Page 19 of 28
D7
D6
D5
D4
D3
D2
D1
D0
2−1
2−2
2−3
2−4
2−5
2−6
8 Bits for Decimal Number
2−7
2−8
AD5235
PROGRAMMING THE VARIABLE RESISTOR
Table 12. RWB (D) at Selected Codes for RAB = 25 kΩ
Rheostat Operation
D (DEC)
1023
512
1
0
The nominal resistance of the RDAC between Terminals A
and B, RAB, is available with 25 kΩ and 250 kΩ with
1024 positions (10-bit resolution). The final digits of the part
number determine the nominal resistance value, for example,
25 kΩ = 25; 250 kΩ = 250.
The 10-bit data-word in the RDAC latch is decoded to select
one of the 1024 possible settings. The following discussion
describes the calculation of resistance RWB at different codes of a
25 kΩ part. The wiper’s first connection starts at Terminal B for
data 0x000. RWB(0) is 50 Ω because of the wiper resistance, and
it is independent of the nominal resistance. The second
connection is the first tap point where RWB(1) becomes 24.4 Ω +
50 Ω = 74.4 Ω for data 0x001. The third connection is the next
tap point representing RWB(2) = 48.8 Ω + 50 Ω = 98.8 Ω for data
0x002, and so on. Each LSB data value increase moves the wiper
up the resistor ladder until the last tap point is reached at
RWB(1023) = 25026 Ω. See Figure 43 for a simplified diagram of
the equivalent RDAC circuit. When RWB is used, Terminal A can
be left floating or tied to the wiper.
Output State
Full scale
Midscale
1 LSB
Zero scale (wiper contact resistor)
Note that, in the zero-scale condition, a finite wiper resistance
of 50 Ω is present. Care should be taken to limit the current
flow between W and B in this state to no more than 20 mA to
avoid degradation or possible destruction of the internal
switches.
Like the mechanical potentiometer that the RDAC replaces, the
AD5235 part is totally symmetrical. The resistance between
Wiper W and Terminal A also produces a digitally controlled
complementary resistance, RWA. Figure 44 shows the symmetrical programmability of the various terminal connections. When
RWA is used, Terminal B can be left floating or tied to the wiper.
Setting the resistance value for RWA starts at a maximum value
of resistance and decreases as the data loaded in the latch is
increased in value.
The general transfer equation for this operation is
100
RWA
RWB
RWA (D) =
1024 − D
× R AB + RW
1024
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75
(2)
For example, the output resistance values in Table 13 are set for
the given RDAC latch codes (applies to RAB = 25 kΩ digital
potentiometers).
50
Table 13. RWA(D) at Selected Codes for RAB = 25 kΩ
D (DEC)
1023
512
1
0
25
0
0
256
512
CODE (Decimal)
768
1023
02816-B-045
RWA(D), RWB(D) (% RWF)
RWB(D) (Ω)
25,026
12,550
74.4
50
Figure 44. RWA(D) and RWB(D) vs. Decimal Code
The general equation that determines the programmed output
resistance between Wx and Bx is
RWA (D) =
D
× R AB + RW
1024
(1)
RWA(D) (Ω)
74.4
12,550
25,026
25,050
Output State
Full scale
Midscale
1 LSB
Zero scale (wiper contact resistance)
The typical distribution of RAB from channel to channel is
±0.2% within the same package. Device-to-device matching is
process lot dependent upon the worst case of ±30% variation.
However, the change in RAB with temperature has a 35 ppm/°C
temperature coefficient.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
where:
D is the decimal equivalent of the data contained in the RDAC
register.
RAB is the nominal resistance between Terminals A and B.
RW is the wiper resistance.
For example, the output resistance values in Table 12 are set for
the given RDAC latch codes (applies to RAB = 25 kΩ digital
potentiometers).
The digital potentiometer can be configured to generate an
output voltage at the wiper terminal that is proportional to the
input voltages applied to Terminals A and B. For example,
connecting Terminal A to 5 V and Terminal B to ground
produces an output voltage at the wiper that can be any value
from 0 V to 5 V. Each LSB of voltage is equal to the voltage
applied across Terminal AB divided by the 2N position
resolution of the potentiometer divider.
Rev. B | Page 20 of 28
AD5235
Because AD5235 can also be supplied by dual supplies, the
general equation defining the output voltage at VW with respect
to ground for any given input voltages applied to Terminals A
and B is
D
VW (D) =
× V AB + V B
1024
Table 16. Restoring the EEMEM Values to RDAC Registers
SDI
0x10XXXX
SDO
0xXXXXXX
0x00XXXX
0x10XXXX
(3)
Equation 3 assumes that VW is buffered so that the effect of
wiper resistance is minimized. Operation of the digital potentiometer in divider mode results in more accurate operation over
temperature. Here, the output voltage is dependent on the ratio
of the internal resistors and not the absolute value; therefore, the
drift improves to 15 ppm/°C. There is no voltage polarity
restriction between Terminals A, B, and W as long as the
terminal voltage (VTERM) stays within VSS < VTERM < VDD.
Table 17. Using Left-Shift by One to Increment 6 dB Steps
SDI
0xC0XXXX
SDO
0xXXXXXX
0xC1XXXX
0xC0XXXX
The following programming examples illustrate a typical
sequence of events for various features of the AD5235. See
Table 7 for the instructions and data-word format. The
instruction numbers, addresses, and data appearing at the SDI
and SDO pins are in hexadecimal format.
SDI
0x32AAAA
SDO
0xXXXXXX
0x335555
0x32AAAA
Table 14. Scratchpad Programming
0xB10200
SDO
0xXXXXXX
Action
Moves Wiper 1 to double the
present data contained in the
RDAC1 register.
Moves Wiper 2 to double the
present data contained in the
RDAC2 register.
Table 18. Storing Additional User Data in EEMEM
PROGRAMMING EXAMPLES
SDI
0xB00100
Action
Restores the EEMEM1 value to the
RDAC1 register.
NOP. Recommended step to minimize
power consumption.
Action
Writes data 0x100 into RDAC1 register,
Wiper W1 moves to 1/4 full-scale
position.
Loads data 0x200 into RDAC2 register,
Wiper W2 moves to 1/2 full-scale
position.
Action
Stores data 0xAAAA in the extra
EEMEM location USER1. (Allowable to
address in 13 locations with a
maximum of 16 bits of data.)
Stores data 0x5555 in the extra
EEMEM location USER2. (Allowable to
address in 13 locations with a
maximum of 16 bits of data.)
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0xB00100
Table 19. Reading Back Data from Memory Locations
SDI
0x92XXXX
SDO
0xXXXXXX
0x00XXXX
0x92AAAA
Table 15. Incrementing RDAC Followed by Storing the
Wiper Setting to EEMEM
SDI
0xB00100
SDO
0xXXXXXX
0xE0XXXX
0xB00100
0xE0XXXX
0xE0XXXX
0x20XXXX
0xXXXXXX
Action
Writes data 0x100 into RDAC1
register, Wiper W1 moves to 1/4 fullscale position.
Increments RDAC1 register by one to
0x101.
Increments RDAC1 register by one to
0x102. Continue until desired wiper
position is reached.
Stores RDAC2 register data into
EEMEM1. Optionally tie WP to GND to
protect EEMEM values.
The EEMEM values for the RDACs can be restored by poweron, by strobing the PR pin, or by the two commands shown in
Table 16.
Action
Prepares data read from USER1
EEMEM location.
NOP Instruction 0 sends a 24-bit word
out of SDO, where the last 16 bits
contain the contents in USER1
EEMEM location. The NOP command
ensures that the device returns to the
idle power dissipation state.
Table 20. Reading Back Wiper Settings
SDI
0xB00200
0xC0XXXX
SDO
0xXXXXXX
0xB00200
0xA0XXXX
0xC0XXXX
0xXXXXXX
0xA003FF
Action
Writes RDAC1 to midscale.
Doubles RDAC1 from midscale to full
scale.
Prepares reading wiper setting from
RDAC1 register.
Reads back full-scale value from SDO.
AD5235EVAL EVALUATION KIT
Analog Devices offers a user-friendly AD5235EVAL evaluation
kit that can be controlled by a personal computer through a
printer port. The driving program is self-contained; no
programming languages or skills are needed.
Rev. B | Page 21 of 28
AD5235
APPLICATIONS
BIPOLAR OPERATION FROM DUAL SUPPLIES
The AD5235 can be operated from dual supplies ±2.5 V, which
enables control of ground referenced ac signals or bipolar
operation. AC signals as high as VDD/VSS can be applied directly
across Terminals A to B with output taken from Terminal W.
See Figure 45 for a typical circuit connection.
Similarly, W–A terminal capacitances are connected to the
output (not shown); their effect at this node is less significant
and the compensation can be avoided in most cases.
+2.5V
µC
GND
SS
VDD
CS
CLK
SDI
SCLK
MOSI
HIGH VOLTAGE OPERATION
A
W
GND
±2.5V p-p
±1.25V p-p
B
AD5235
VSS
D = MIDSCALE
–2.5V
02816-B-046
VDD
mum value. Doing this might overcompensate and compromise
the performance when R2 is set at low values. On the other
hand, it avoids the ringing or oscillation at the worst case. For
critical applications, C2 should be found empirically to suit the
need. In general, C2 in the range of a few pF to no more than a
few tenths of pF is usually adequate for the compensation.
The digital potentiometer can be placed directly in the feedback
or input path of an op amp for gain control, provided that the
voltage across Terminals A–B, W–A, or W–B does not exceed
|5 V|. When high voltage gain is needed, users should set a fixed
gain in an op amp and let the digital potentiometer control the
adjustable input. Figure 47 shows a simple implementation.
C
Figure 45. Bipolar Operation from Dual Supplies
R
2R
GAIN CONTROL COMPENSATION
15V
A digital potentiometer is commonly used in gain control such
as the noninverting gain amplifier shown in Figure 46.
V+
5V
VO
A1
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AD5235
C2
2.2pF
Figure 47. 15 V Voltage Span Control
A
Similarly, a compensation capacitor C might be needed to
dampen the potential ringing when the digital potentiometer
changes steps. This effect is prominent when stray capacitance
at the inverted node is augmented by a large feedback resistor.
Usually, a pF Capacitor C is adequate to combat the problem.
W
Vi
VO
02816-B-047
U1
Figure 46. Typical Noninverting Gain Amplifier
DAC
When RDAC B terminal parasitic capacitance is connected to
the op amp noninverting node, it introduces a zero for the 1/ϐO
term with 20 dB/dec, while a typical op amp GBP has
−20 dB/dec characteristics. A large R2 and finite C1 can cause
this zero’s frequency to fall well below the crossover frequency.
Therefore, the rate of closure becomes 40 dB/dec, and the
system has a 0° phase margin at the crossover frequency. The
output can ring or oscillate, if an input is a rectangular pulse or
step function. Similarly, it is also likely to ring when switching
between two gain values; this is equivalent to a stop change at
the input.
For DAC operation (Figure 48), it is common to buffer the
output of the digital potentiometer unless the load is much
larger than RWB. The buffer serves the purpose of impedance
conversion and can drive heavier loads.
Depending on the op amp GBP, reducing the feedback resistor
might extend the zero’s frequency far enough to overcome the
problem. A better approach is to include a compensation
capacitor, C2, to cancel the effect caused by C1. Optimum
compensation occurs when R1 × C1 = R2 × C2. This is not an
option because of the variation of R2. As a result, one can use
the relationship above and scale C2 as if R2 were at its maxiRev. B | Page 22 of 28
5V
1 U1
VIN
AD5235
VOUT
GND
2
5V
3
A
B
AD1582
W
V+
AD8601
V–
A1
Figure 48. Unipolar 10-Bit DAC
VO
02816-B-049
B
C1
11pF
0V TO 15V
B
R2
250kΩ
R1
47kΩ
V–
W
02816-A-048
A
AD5235
BIPOLAR PROGRAMMABLE GAIN AMPLIFIER
For applications requiring bipolar gain, Figure 49 shows one
implementation. Digital potentiometer U1 sets the adjustment
range; the wiper voltage VW2 can, therefore, be programmed
between Vi and −KVi at a given U2 setting. Configure A2 as a
noninverting amplifier that yields a transfer function:
VO ⎛ R2 ⎞ ⎛ D 2
= ⎜1 +
× (1 + K ) − K ⎞⎟
⎟×⎜
VI ⎝
R1 ⎠ ⎝ 1024
⎠
nonvolatile memory feature that in some cases outweighs any
shortfall in precision.
Without consideration of the wiper resistance, the output of this
circuit is approximately
⎞
⎛ 2D 2
VO = ⎜
− 1⎟ × V REF
⎝ 1024 ⎠
(6)
(4)
+2.5V
U2
where K is the ratio of RWB1/RWA1 set by U1.
V+
AD8552
W2
AD5235
A2
2 U3
V+
W
U2
Vi
OP2177
+2.5VREF
R2
A2
A1
Vi
B1
W1
VIN VOUT
VO
V–
B2
6
C
TRIM
GND
VSS
5
B2
A2
A1
B1
VDD
A2
+2.5V
W1
U1
–2.5VREF
–2.5V
V+
AD8552
ADR421
–kVi
VO
V–
V–
R1
U1 = U2 = AD5235
02816-B-051
VDD
A1
V+
OP2177
U1
V–
A
–2.5V
U1 = MIDSCALE
02816-B-050
AD5235
VSS
Figure 50. 10-Bit Bipolar DAC
PROGRAMMABLE VOLTAGE SOURCE WITH
BOOSTED OUTPUT
Figure 49. Bipolar Programmable Gain Amplifier
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R2 ⎞
VO = ⎛⎜1 +
⎟
R1 ⎠
⎝
⎞
⎛ 2D 2
− 1⎟ × Vi
⎜
1024
⎠
⎝
For applications that require high current adjustment, such as a
laser diode driver or tunable laser, a boosted voltage source can
be considered (see Figure 51).
(5)
VIN
VOUT
2N7002
AD5235
Table 21 shows the result of adjusting D2, with A2 configured as
a unity gain, a gain of 2, and a gain of 10. The result is a bipolar
amplifier with linearly programmable gain and 1024-step
resolution.
A
B
SIGNAL CC
U2
W
RBIAS
IL
V+
AD8601
LD
V–
Table 21. Result of Bipolar Gain Amplifier
D
0
256
512
768
1023
R1 = ∞, R2 = 0
−1
−0.5
0
0.5
0.992
R1 = R2
−2
−1
0
1
1.984
R2 = 9 R1
−10
−5
0
5
9.92
10-BIT BIPOLAR DAC
If the circuit in Figure 49 is changed with the input taken from a
precision reference, U1 is set to midscale, and A2 is configured
as a buffer, a 10-bit bipolar DAC can be realized (Figure 48).
Compared to the conventional DAC, this circuit offers
comparable resolution, but not the precision because of the
wiper resistance effects. Degradation of the nonlinearity and
temperature coefficient is prominent near the low values of the
adjustment range. On the other hand, this circuit offers a unique
02816-B-052
In the simpler (and much more usual) case where K = 1, VO is
simplified to
Figure 51. Programmable Booster Voltage Source
In this circuit, the inverting input of the op amp forces the VOUT
to be equal to the wiper voltage set by the digital potentiometer.
The load current is then delivered by the supply via the N-Ch
FET N1. N1 power handling must be adequate to dissipate
(Vi − VO) × IL power. This circuit can source a maximum of
100 mA with a 5 V supply.
For precision applications, a voltage reference such as ADR421,
ADR03, or ADR370 can be applied at Terminal A of the digital
potentiometer.
Rev. B | Page 23 of 28
AD5235
R1
150kΩ
PROGRAMMABLE CURRENT SOURCE
R2
15kΩ
A programmable current source can be implemented with the
circuit shown in Figure 52.
+15V
+5V
+2.5V
VIN
3
SLEEP VOUT
6
0 TO (2.048 + VL)
GND
+
AD5235
B
W
B
1µF
W
V+
R2A
14.95kΩ
VL
RL
500Ω
IL
–
U2
+
VL
RL
100Ω
IL
02861-B-053
V–
–5V
Figure 52. Programmable Current Source
REF191 is a unique low supply headroom and high current
handling precision reference that can deliver 20 mA at 2.048 V.
The load current is simply the voltage across Terminals B–W of
the digital potentiometer divided by RS:
IL =
–15V
R1
150kΩ
Figure 53. Programmable Bidirectional Current Source
OP1177
–2.048V TO VL
R2B
50Ω
A1
–15V
+5V
AD5235
V+
OP2177
– V–
–2.5V
RS
102Ω
A
4
+15V
A
REF191
C1
V+
OP2177
+ V– A2
02816-B-054
U1
V REF × D
R S × 1024
R2B, in theory, can be made as small as necessary to achieve the
current needed within the A2 output current-driving capability.
In this circuit, OP2177 delivers ±5 mA in either direction, and
the voltage compliance approaches 15 V. Without the additions
of C1 and C2, the output impedance (looking into VL) can be
shown as
Z0 =
R1' R2B (R1 + R2A)
(9)
R1 R2' − R1' (R2A + R2B)
ZO can be infinite, if resistors R1' and R2' match precisely with
R1 and R2A + R2B, respectively, which is desirable. On the other
hand, ZO can be negative, if the resistors are not matched and
cause oscillation. As a result, C1, in the range of a few pF, is
needed to prevent oscillation from the negative impedance.
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(7)
The circuit is simple, but be aware that there are two issues.
First, dual-supply op amps are ideal, because the ground
potential of REF191 can swing from −2.048 V at zero scale to VL
at full scale of the potentiometer setting. Although the circuit
works under single supply, the programmable resolution of the
system is reduced by half. Second, the voltage compliance at VL
is limited to 2.5 V or equivalently a 125 Ω load. Should higher
voltage compliance be needed, users can consider digital
potentiometers AD5260, AD5280, and AD7376. Figure 53 shows
an alternate circuit for high voltage compliance.
PROGRAMMABLE LOW-PASS FILTER
In analog-to-digital conversions, it is common to include an
antialiasing filter to band limit the sampling signal. The dualchannel AD5235 can, therefore, be used to construct a secondorder Sallen-Key low-pass filter, as shown in Figure 54.
C1
+2.5V
To achieve higher current, such as when driving a high power
LED, the user can replace the U1 with an LDO, reduce RS, and
add a resistor in series with the digital potentiometer’s
A terminal. This limits the potentiometer’s current and
increases the current adjustment resolution.
R1
Vi
B
B
V+
W
AD8601
A
W
R
R
–2.5V
ADJUSTED
CONCURRENTLY
For applications that require bidirectional current control or
higher voltage compliance, a Howland current pump can be a
solution (Figure 53). If the resistors are matched, the load
current is
VO
V–
U1
C2
PROGRAMMABLE BIDIRECTIONAL CURRENT
SOURCE
R2 A + R 2 B
R1
IL =
× VW
R2 B
A
R2
02816-B-055
2
–
C1
10pF
Figure 54. Sallen-Key Low-Pass Filter
The design equations are
(8)
Rev. B | Page 24 of 28
VO
=
Vi
ωf 2
ωf
S2 +
S+ωf 2
Q
(10)
AD5235
1
R1 R2 C1 C2
ωO =
Q=
(11)
1
1
+
R1 C1 R2 C2
PROGRAMMABLE OSCILLATOR
In a classic Wien-bridge oscillator, shown in Figure 55, the Wien
network (R, R'C, C') provides positive feedback, while R1 and
R2 provide negative feedback.
FREQUENCY
ADJUSTMENT
R'
25kΩ
C'
VP
B
R
25kΩ
A
2
VO = I D R2B + V D
3
(12)
Users can first select some convenient values for the capacitors.
To achieve maximally flat bandwidth, where Q = 0.707, let C1 be
twice the size of C2 and let R1 equal R2. As a result, the user can
adjust R1 and R2 concurrently to the same setting to achieve the
desirable bandwidth.
C
2.2nF
Once the frequency is set, the oscillation amplitude can be
turned by R2B, because
A
W
+2.5V
2.2nF
W
+
B
VO, ID, and VD are interdependent variables. With proper
selection of R2B, an equilibrium is reached such that VWF
converges. R2B can be in series with a discrete resistor to
increase the amplitude, but the total resistance cannot be too
large to saturate the output.
In both circuits shown in Figure 54 and Figure 55, the frequency
tuning requires that both RDACs be adjusted concurrently to
the same settings. Because the two channels might be adjusted
one at a time, an intermediate state occurs that might not be
acceptable for some applications. Of course, the increment/
decrement instructions (5, 7, 13, and 15) can all be used.
Different devices can also be used in daisy-chain mode so that
parts can be programmed to the same settings simultaneously.
OPTICAL TRANSMITTER CALIBRATION WITH
ADN2841
U1
V+
VO
OP1177
– V–
–2.5V
(16)
The AD5235, together with the multirate 2.7 Gbps laser diode
driver ADN2841, forms an optical supervisory system in which
the dual digital potentiometers can be used to set the laser
average optical power and extinction ratio (Figure 56). AD5235
is particularly suited for the optical parameter settings because
of its high resolution and superior temperature coefficient
characteristics.
R2A
2.1kΩ
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R2B
10kΩ
B
W
R1
1kΩ
A
D1
D2
AMPLITUDE
ADJUSTMENT
02816-B-056
R = R' = AD5235
R2B = AD5231
D1 = D2 = 1N4148
VCC
VCC
Figure 55. Programmable Oscillator with Amplitude Control
At the resonant frequency, fO, the overall phase shift is zero, and
the positive feedback causes the circuit to oscillate. With R = R',
RDAC1
CS
CLK
A1
B1
EEMEM
A2
B2
DIN
ERSET
DIN
DINQ
IDTONE
(14)
At resonance, setting
R2
=2
R1
IBIAS
W2
Figure 56. Optical Supervisory System
(15)
balances the bridge. In practice, R2/R1 should be set slightly
larger than 2 to ensure that the oscillation can start. On the
other hand, the alternate turn-on of the diodes D1 and D2
ensures that R2/R1 is smaller than 2, momentarily stabilizing
the oscillation.
The ADN2841 is a 2.7 Gbps laser diode driver that uses a
unique control algorithm to manage the laser’s average power
and extinction ratio after the laser’s initial factory calibration.
The ADN2841 stabilizes the laser’s data transmission by
continuously monitoring its optical power and correcting the
variations caused by temperature and the laser’s degradation
over time. In the ADN2841, the IMPD monitors the laser diode
current. Through its dual loop power and extinction ratio
Rev. B | Page 25 of 28
02816-B-057
1024 − D
R AB
1024
IMODP
SDI
where R is equal to RWA such that
R=
PSET
CONTROL
RDAC2
(13)
ADN2841
IDTONE
1
1
or f O =
ωO =
RC
2πRC
EEMEM
W1
DINQ
C = C', and R2 = R2A /(R2B + RDIODE), the oscillation frequency
is
IMPD
AD5235
AD5235
A1
A1
W1
B2
W2
02816-B-058
B1
A2
Figure 57. Reduce Resistance by Half with Linear Adjustment Characteristics
R
Figure 59. Resistor Scaling with Pseudo Log Adjustment Characteristics
The equation is approximated as
R eq =
RESISTANCE SCALING
The AD5235 offers 25 kΩ or 250 kΩ nominal resistance. For
users who need lower resistance but must still maintain the
number of adjustment steps, they can parallel multiple devices.
For example, Figure 57 shows a simple scheme of paralleling
two channels of RDACs. To adjust half the resistance linearly
per step, users need to program both RDACs concurrently with
the same settings.
W1
B1
02816-B-060
control calibrated by the AD5235’s dual RDACs, the internal
driver controls the bias current, IBIAS, and consequently the
average power. It also regulates the modulation current, IMODP,
by changing the modulation current linearly with slope
efficiency. Any changes in the laser threshold current or slope
efficiency are, therefore, compensated. As a result, this optical
supervisory system minimizes the laser characterization efforts
and, therefore, enables designers to apply comparable lasers
from multiple sources.
D × R AB + 51200
(18)
D × R AB + 51200 + 1024 × R
Users should also be aware of the need for tolerance matching
as well as for temperature coefficient matching of the
components.
RESISTANCE TOLERANCE, DRIFT, AND
TEMPERATURE COEFFICIENT MISMATCH
CONSIDERATIONS
In a rheostat mode operation such as gain control (see
Figure 60), the tolerance mismatch between the digital potentiometer and the discrete resistor can cause repeatability issues
among various systems. Because of the inherent matching of the
silicon process, it is practical to apply the dual-channel device in
this type of application. As such, R1 can be replaced by one of
the channels of the digital potentiometer and programmed to a
specific value. R2 can be used for the adjustable gain. Although
it adds cost, this approach minimizes the tolerance and
temperature coefficient mismatch between R1 and R2. This
approach also tracks the resistance drift over time. As a result,
these less than ideal parameters become less sensitive to system
variations.
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In voltage divider mode, by paralleling a discrete resistor as
shown in Figure 58, a proportionately lower voltage appears at
Terminal A-to-B. This translates into a finer degree of precision,
because the step size at Terminal W is smaller. The voltage can
be found as follows:
VW (D) =
(RAB // R2 )
D
×
× VDD
R3 + RAB // R2 1024
(17)
B R2 A
W
VDD
C1
R1*
–
AD8601
Vi
+
U1
W
B
0
* REPLACED WITH ANOTHER
CHANNEL OF RDAC
02816-B-059
R2
A
R1
VO
02816-B-061
R3
Figure 60. Linear Gain Control with Tracking Resistance Tolerance, Drift,
and Temperature Coefficient
Figure 58. Lowering the Nominal Resistance
Figure 57 and Figure 58 show that the digital potentiometers
change steps linearly. On the other hand, pseudolog taper
adjustment is usually preferred in applications such as audio
control. Figure 59 shows another type of resistance scaling. In
this configuration, the smaller the R2 with respect to RAB, the
more the pseudolog taper characteristic of the circuit behaves.
Note that the circuit in Figure 61 can track tolerance,
temperature coefficient, and drift in this particular application.
The characteristic of the transfer function is, however, a pseudologarithmic rather than a linear gain function.
Rev. B | Page 26 of 28
AD5235
A
R
RDAC
25kΩ
B
B
A
C1
W
CB
11pF
CA
11pF
+
U1
VO
80pF
02816-B-062
Vi
W
Figure 61. Nonlinear Gain Control with Tracking Resistance Tolerance
and Drift
02816-B-063
–
AD8601
Figure 62. RDAC Circuit Simulation Model (RDAC = 25 kΩ)
The following code provides a macro model net list for the
25 kΩ RDAC:
RDAC CIRCUIT SIMULATION MODEL
The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the RDACs. Configured
as a potentiometer divider, the −3 dB bandwidth of the AD5235
(25 kΩ resistor) measures 125 kHz at half-scale. Figure 14
provides the large signal BODE plot characteristics of the two
available resistor versions, 25 kΩ and 250 kΩ. A parasitic
simulation model is shown in Figure 62.
.PARAM D = 1024, RDAC = 25E3
*
.SUBCKT DPOT (A, W, B)
*
CA
A
0
11E-12
RWA A
W
{(1-D/1024)* RDAC + 50}
CW
W
0
80E-12
RWB W
B
{D/1024 * RDAC + 50}
CB
B
0
11E-12
*
.ENDS DPOT
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Rev. B | Page 27 of 28
AD5235
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.30
0.19
0.65
BSC
COPLANARITY
0.10
8°
0°
SEATING
PLANE
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153AB
Figure 63. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD5235BRU25
AD5235BRU25-RL7
AD5235BRUZ252
AD5235BRUZ25-RL72
AD5235BRU250
AD5235BRU250-RL7
AD5235BRUZ2502
AD5235BRUZ250-RL72
AD5235EVAL25
AD5235EVAL250
R WB_FS
(kΩ)
25
25
25
25
250
250
250
250
25
250
RDNL
±2
±2
±2
±2
±2
±2
±2
±2
RINL
±4
±4
±4
±4
±4
±4
±4
±4
Temperature
Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package
Description
TSSOP-16
TSSOP-16
TSSOP-16
TSSOP-16
TSSOP-16
TSSOP-16
TSSOP-16
TSSOP-16
Package
Option
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
Ordering
Quantity
96
1,000
96
1,000
96
1,000
96
1,000
1
1
Branding1
5235B25
5235B25
5235B25
5235B25
5235B250
5235B250
5235B250
5235B250
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1
Line 1 contains the ADI logo followed by the date code, YYWW. Line 2 contains the model number followed by the end-to-end resistance value (note: D = 250 kΩ).
—OR—
Line 1 contains the model number. Line 2 contains the ADI logo followed by the end-to-end resistance value. Line 3 contains the date code, YYWW.
2
Z = Pb-free part.
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02816–0–7/04(B)
Rev. B | Page 28 of 28
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