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AD5390 数据手册DataSheet 下载
8-/16-Channel, 3 V/5 V, Serial Input,
Single-Supply, 12-/14-Bit Voltage Output
AD5390/AD5391/AD5392
FEATURES
I2C-compatible interface
Integrated functions
channel monitor
simultaneous output update via LDAC
clear function to user-programmable code
amplifier boost mode to optimize slew rate
user-programmable offset and gain adjust
toggle mode enables square wave generation
thermal monitor
AD5390: 16-channel, 14-bit voltage output DAC
AD5391: 16-channel, 12-bit voltage output DAC
AD5392: 8-channel, 14-bit voltage output DAC
Guaranteed monotonic
INL
±1 LSB max (AD5391)
±3 LSB max (AD5390-5/AD5392-5)
±4 LSB max (AD5390-3/AD5392-3)
On-chip 1.25 V/2.5 V, 10 ppm/°C reference
Temperature range: −40°C to +85°C
Rail-to-rail output amplifier
Power-down mode
Package types
64-lead LFCSP (9 mm × 9 mm)
52-lead LQFP (10 mm × 10 mm)
User interfaces
Serial SPI-, QSPI-, MICROWIRE-, and DSP-compatible
(featuring data readback)
APPLICATIONS
Instrumentation and industrial control
Power amplifier control
Level setting (ATE)
Control systems
Microelectromechanical systems (MEMs)
Variable optical attenuators (VOAs)
Optical transceivers (MSA 300, XFP)
FUNCTIONAL BLOCK DIAGRAM
DVDD (×3)
DGND (×3/×4)
AVDD (×2)
AGND (×2)
DAC_GND (×2)
14
DCEN/AD1
INPUT
REG
0
DIN/SDA
SYNC/AD0
STATE
MACHINE
AND
CONTROL
LOGIC
INTERFACE
CONTROL
LOGIC
SDO
INPUT
REG
1
DAC
REG
0
14
DAC 0
VOUT 0
m REG0
14
14
14
14
14
SCLK/SCL
REFOUT/REFIN SIGNAL_GND (×2)
1.25V/2.5V
REFERENCE
AD5390
SPI/I2C
REF_GND
c REG0
14
14
14
R
DAC
REG
1
14
DAC 1
VOUT 1
VOUT 2
m REG1
14
c REG1
R
BUSY
R
VOUT 3
VOUT 4
PD
14
CLR
RESET
R
VIN15
INPUT
REG
7
14
MON_IN1
MUX
MON_IN2
14
DAC
REG
6
14
VOUT 5
DAC 6
VOUT 6
m REG6
14
14
14
14
14
POWER-ON
RESET
VIN0
INPUT
REG
6
c REG6
R
14
14
DAC
REG
7
14
R
DAC 7
VOUT 7
m REG7
c REG7
VOUT 8
R
×2
R
LDAC
MON_OUT
03773-001
VOUT 15
Figure 1.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
AD5390/AD5391/AD5392
TABLE OF CONTENTS
Features .............................................................................................. 1 I2C Serial Interface ..................................................................... 26 Applications ....................................................................................... 1 I2C Write Operation ....................................................................... 27 Functional Block Diagram .............................................................. 1 4-Byte Mode ................................................................................ 27 Revision History ............................................................................... 2 3-Byte Mode ................................................................................ 28 General Description ......................................................................... 3 2-Byte Mode ................................................................................ 29 Specifications..................................................................................... 4 AD539x On-Chip Special Function Registers ........................ 30 AD5390-5/AD5391-5/AD5392-5 Specifications ..................... 4 Control Register Write............................................................... 32 AD5390-5/AD5391-5/AD5392-5 AC Characteristics............. 6 Hardware Functions ....................................................................... 34 AD5390-3/AD5391-3/AD5392-3 Specifications ..................... 7 Reset Function ............................................................................ 34 AD5390-3/AD5391-3/AD5392-3 AC Characteristics............. 9 Asynchronous Clear Function.................................................. 34 Timing Characteristics................................................................... 10 BUSY and LDAC Functions...................................................... 34 Serial SPI-, QSPI-, MICROWIRE-, and DSP-Compatible
Interface ....................................................................................... 10 Power-On Reset .......................................................................... 34 I2C Serial Interface...................................................................... 12 Absolute Maximum Ratings.......................................................... 13 ESD Caution ................................................................................ 13 Pin Configuraton and Function Descriptions ............................ 14 Terminology .................................................................................... 17 Typical Performance Characteristics ........................................... 18 Functional Description .................................................................. 22 DAC Architecture ....................................................................... 22 Data Decoding ............................................................................ 23 Interfaces .......................................................................................... 24 Power-Down ............................................................................... 34 Microprocessor Interfacing ....................................................... 34 Application Information ................................................................ 36 Power Supply Decoupling ......................................................... 36 Typical Configuration Circuit .................................................. 36 AD539x Monitor Function ....................................................... 37 Toggle Mode Function............................................................... 37 Thermal Monitor Function ....................................................... 37 Outline Dimensions ....................................................................... 39 Ordering Guide .......................................................................... 40 DSP-, SPI-, and MICROWIRE-Compatible Serial
Interface ....................................................................................... 24 REVISION HISTORY
1/09—Rev. B to Rev. C
Updated Format .................................................................. Universal
Changes to Figure 33 ...................................................................... 27
Added Figure 34 and renumbered sequentially ......................... 27
Changes to Figure 34 ...................................................................... 28
Changes to Table 28 ........................................................................ 33
Change order of Figure 41 and Figure 42 .................................... 36
Changes to Toggle Mode Function Section ................................ 37
3/06—Rev. A to Rev. B
Changes to Figure 1 .......................................................................... 1
Changes to Table 9 .......................................................................... 14
Changes to Table 12 and Table 15 ................................................ 23
Updated Outline Dimensions ....................................................... 39
Changes to Ordering Guide .......................................................... 40
10/04—Rev. 0 to Rev. A
Changes to Features ..........................................................................1
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................4
Changes to Table 3.............................................................................6
Changes to Table 4.............................................................................7
Changes to Figure 36...................................................................... 35
Changes to Figure 37...................................................................... 36
Changes to Figure 38...................................................................... 36
Changes to Ordering Guide .......................................................... 41
4/04—Revision 0: Initial Version
Rev. C | Page 2 of 40
AD5390/AD5391/AD5392
GENERAL DESCRIPTION
The AD5390/AD5391 are complete single-supply, 16-channel,
14-bit and 12-bit DACs, respectively. The AD5392 is a complete
single-supply, 8-channel, 14-bit DAC. The devices are available
in either a 64-lead LFCSP or a 52-lead LQFP. All channels have
an on-chip output amplifier with rail-to-rail operation. All
devices include an internal 1.25/2.5 V, 10 ppm/°C reference, an
on-chip channel monitor function that multiplexes the analog
outputs to a common MON_OUT pin for external monitoring,
and an output amplifier boost mode that optimizes the output
amplifier slew rate.
The AD5390/AD5391/AD5392 contain a 3-wire serial interface
with interface speeds in excess of 30 MHz that are compatible
with SPI®, QSPI™, MICROWIRE™, and DSP interface standards
and an I2C-compatible interface supporting a 400 kHz data
transfer rate.
An input register followed by a DAC register provides doublebuffering, allowing DAC outputs to be updated independently
or simultaneously using the LDAC input. Each channel has a
programmable gain and offset adjust register, letting the user
fully calibrate any DAC channel.
Power consumption is typically 0.25 mA per channel.
Table 1. Additional High Channel Count, Low Voltage, Single-Supply DACs in Portfolio
Model
AD5380BST-5
AD5380BST-3
AD5384BBC-5
AD5384BBC-3
AD5381BST-5
AD5381BST-3
AD5382BST-5
AD5382BST-3
AD5383BST-5
AD5383BST-3
Resolution
14 Bits
14 Bits
14 Bits
14 Bits
12 Bits
12 Bits
14 Bits
14 Bits
12 Bits
12 Bits
AVDD Range
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
Output Channels
40
40
40
40
40
40
32
32
32
32
Linearity Error (LSB)
±4
±4
±4
±4
±1
±1
±4
±4
±1
±1
Rev. C | Page 3 of 40
Package Description
100-Lead LQFP
100-Lead LQFP
100-Lead CSPBGA
100-Lead CSPBGA
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
Package Option
ST-100
ST-100
BC-100
BC-100
ST-100
ST-100
ST-100
ST-100
ST-100
ST-100
AD5390/AD5391/AD5392
SPECIFICATIONS
AD5390-5/AD5391-5/AD5392-5 SPECIFICATIONS
AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V; REFIN = 2.5 V external. All specifications TMIN to TMAX,
unless otherwise noted.
Table 2.
Parameter
ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Offset Error
Offset Error TC
Gain Error
Gain Temperature Coefficient 2
DC Crosstalk2
REFERENCE INPUT/OUTPUT
Reference Input2
Reference Input Voltage
DC Input Impedance
Input Current
Reference Range
Reference Output 3
Output Voltage
Reference TC
Output Impedance
OUTPUT CHARACTERISTICS2
Output Voltage Range 4
Short-Circuit Current
Load Current
Capacitive Load Stability
RL = ∞
RL = 5 kΩ
DC Output Impedance
MONITOR OUTPUT PIN
Output Impedance
Three-State Leakage Current
LOGIC INPUTS2
VIH, Input High Voltage
VIL, Input Low Voltage
Input Current
Pin Capacitance
AD5390-5 1
AD5392-51
AD5391-51
Unit
14
±3
−1/+2
4
±4
±5
±0.024
±0.06
2
0.5
12
±1
±1
4
±4
±5
±0.024
±0.06
2
0.5
Bits
LSB max
LSB max
mV max
mV max
μV/°C typ
% FSR max
% FSR max
ppm FSR/°C typ
LSB max
2.5
2.5
V
1
±1
1 V to AVDD/2
1
±1
1 V to AVDD/2
MΩ min
μA max
V min/max
2.495/2.505
1.22/1.28
±10
±15
2.2
2.495/2.505
1.22/1.28
±10
±15
2.2
V min/max
V min/max
ppm max
ppm max
kΩ typ
0/AVDD
40
±1
0/AVDD
40
±1
V min/max
mA max
mA max
200
1000
0.5
200
1000
0.5
pF max
pF max
Ω max
500
100
500
100
Ω typ
nA typ
2
0.8
±10
10
2
0.8
±10
10
V min
V max
μA max
pF max
Test Conditions/Comments
Guaranteed monotonic over temperature
Measured at code 32 in the linear region
At 25°C TMIN to TMAX
±1% for specified performance,
AVDD = 2 × REFIN + 50 mV
Typically 100 MΩ
Typically ±30 nA
Enabled via internal/external bit in control
register; REF select bit in control register
selects the reference voltage
At ambient, optimized for 2.5 V operation
At ambient when 1.25 V reference is selected
Temperature range: 25°C to 85°C
Temperature range: −40°C to +85°C
DVDD = 2.7 V to 5.5 V
Rev. C | Page 4 of 40
Total for all pins, TA = TMIN to TMAX
AD5390/AD5391/AD5392
AD5390-5 1
AD5392-51
AD5391-51
Unit
Test Conditions/Comments
0.7 DVDD
0.3 DVDD
±1
0.05 DVDD
8
50
0.7 DVDD
0.3 DVDD
±1
0.05 DVDD
8
50
V min
V max
μA max
V min
pF typ
ns max
SMBus-compatible at DVDD < 3.6 V
SMBus-compatible at DVDD < 3.6 V
0.4
DVDD − 1
0.4
DVDD − 0.5
±1
5
0.4
DVDD − 1
0.4
DVDD − 0.5
±1
5
V max
V min
V max
V min
μA max
pF typ
DVDD = 5 V ± 10%, sinking 200 μA
DVDD = 5 V ± 10%, SDO only, sourcing 200 μA
DVDD = 2.7 V to 3.6 V, sinking 200 μA
DVDD = 2.7 V to 3.6 V SDO only, sourcing 200 μA
0.4
0.6
±1
8
0.4
0.6
±1
8
V max
V max
μA max
pF typ
ISINK = 3 mA
ISINK = 6 mA
4.5/5.5
2.7/5.5
4.5/5.5
2.7/5.5
V min/max
V min/max
−85
0.375
−85
0.375
AIDD
0.475
0.475
DIDD
AIDD (Power-Down)
DIDD (Power-Down)
Power Dissipation
1
1
20
35
1
1
20
35
dB typ
mA/channel
max
mA/channel
max
mA max
μA max
μA max
mW max
20
20
mW max
Parameter
LOGIC INPUTS (SCL, SDA Only)
VIH, Input High Voltage
VIL, Input Low Voltage
IIN, Input Leakage Current
VHYST, Input Hysteresis
CIN, Input Capacitance
Glitch Rejection
LOGIC OUTPUTS (BUSY, SDO)2
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
High Impedance Leakage Current
High Impedance Output Capacitance
LOGIC OUTPUT (SDA)2
VOL, Output Low Voltage
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
AVDD
DVDD
Power Supply Sensitivity2
∆Midscale/∆AVDD
AIDD
1
Input filtering suppresses noise spikes of <50 ns
Outputs unloaded, boost off,
0.25 mA/channel typ
Outputs unloaded, boost on,
0.325 mA/channel typ
VIH = DVDD, VIL = DGND
Typically 200 nA
Typically 3 μA
AD5390/AD5391 with outputs unloaded,
AVDD = DVDD = 5 V, boost off
AD5392 with outputs unloaded,
AVDD = DVDD = 5 V, boost off
AD539x-5 products are calibrated with a 2.5 V reference. Temperature range for all versions: −40°C to +85°C.
Guaranteed by characterization, not production tested.
3
Programmable either to 1.25 V typical or 2.5 V typical via the AD539x control register. Operating the AD539x-5 products with a reference of 1.25 V leads to a
degradation in performance accuracy.
4
Accuracy guaranteed from VOUT = 10 mV to AVDD − 50 mV.
2
Rev. C | Page 5 of 40
AD5390/AD5391/AD5392
AD5390-5/AD5391-5/AD5392-5 AC CHARACTERISTICS
AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V.
Table 3.
Parameter
DYNAMIC PERFORMANCE
Output Voltage Settling Time
AD5390/AD5392
AD5391
Slew rate 2
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Channel-to-Channel Isolation
DAC-to-DAC Crosstalk
Digital Crosstalk
Digital Feedthrough
Output Noise (0.1 Hz to 10 Hz)
Output Noise Spectral Density
@ 1 kHz
@ 10 kHz
1
2
All 1
Unit
Test Conditions/Comments
8
10
6
8
3
2
12
15
100
1
0.8
0.1
15
40
μs typ
μs max
μs typ
μs max
V/μs typ
V/μs typ
nV-s typ
mV typ
dB typ
nV-s typ
nV-s typ
nV-s typ
μV p-p typ
μV p-p typ
¼ scale to ¾ scale change settling to ±1 LSB
150
100
nV/(Hz)1/2 typ
nV/(Hz)1/2 typ
¼ scale to ¾ scale change settling to ±1 LSB
Boost mode on
Boost mode off
See the Terminology section
See the Terminology section
Effect of input bus activity on DAC output under test
External reference midscale loaded to DAC
Internal reference midscale loaded to DAC
Guaranteed by characterization, not production tested.
The slew rate can be adjusted via the current boost control bit in the DAC control register.
Rev. C | Page 6 of 40
AD5390/AD5391/AD5392
AD5390-3/AD5391-3/AD5392-3 SPECIFICATIONS
AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V; REFIN = 1.25 V external. All specifications TMIN to TMAX,
unless otherwise noted.
Table 4.
Parameter
ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Offset Error
Offset Error TC
Gain Error
Gain Temperature Coefficient2
DC Crosstalk
REFERENCE INPUT/OUTPUT
Reference Input 2
Reference Input Voltage
DC Input Impedance
Input Current
Reference Range
Reference Output 3
Output Voltage
Reference TC
Output Impedance
OUTPUT CHARACTERISTICS2
Output Voltage Range 4
Short-Circuit Current
Load Current
Capacitive Load Stability
RL = ∞
RL = 5 kΩ
DC Output Impedance
MONITOR OUTPUT PIN2
Output Impedance
Three-State Leakage Current
LOGIC INPUTS2
VIH, Input High Voltage
VIL, Input Low Voltage
Input Current
Pin Capacitance
Logic Inputs (SCL, SDA Only)
VIH, Input High Voltage
VIL, Input Low Voltage
IIN, Input Leakage Current
VHYST, Input Hysteresis
Glitch Rejection
AD5390-3 1
AD5392-31
AD5391-31
Unit
14
±4
−1/+2
4
±4
±5
±0.024
±0.1
2
0.5
12
±1
±1
4
±4
±5
±0.024
±0.1
2
0.5
Bits
LSB max
LSB max
mV max
mV max
μV/°C typ
% FSR max
% FSR max
ppm FSR/°C typ
mV max
1.25
1
±1
1 V to AVDD/2
1.25
1
±1
1 V to AVDD/2
V
MΩ min
μA max
V min/max
1.245/1.255
2.47/2.53
±10
±15
2.2
1.245/1.255
2.47/2.53
±10
±15
2.2
V min/max
V min/max
ppm max
ppm max
kΩ typ
0/AVDD
40
±1
0/AVDD
40
±1
V min/max
mA max
mA max
200
1000
0.5
200
1000
0.5
pF max
pF max
Ω max
500
100
500
100
Ω typ
nA typ
2
0.8
±10
10
2
0.8
±10
10
V min
V max
μA max
pF max
0.7 DVDD
0.3 DVDD
±1
0.05 DVDD
50
0.7 DVDD
0.3 DVDD
±1
0.05 DVDD
50
V min
V max
μA max
V min
ns max
Test Conditions/Comments
Guaranteed monotonic over temperature
Measured at code 64 in the linear region
At 25°C
TMIN to TMAX
±1% for specified performance
Typically 100 MΩ
Typically ±30 nA
Enabled via internal/external bit in control
register; REF select bit in control register
selects the reference voltage
At ambient, optimized for 1.25 V operation
At ambient when 2.5 V reference is selected
Temperature range: 25°C to 85°C
Temperature range: −40°C to +85°C
DVDD = 2.7 V to 5.5 V
Rev. C | Page 7 of 40
Total for all pins. TA = TMIN to TMAX
SMBus-compatible at DVDD < 3.6 V
SMBus-compatible at DVDD < 3.6 V
Input filtering suppresses noise spikes <50 ns
AD5390/AD5391/AD5392
AD5390-3 1
AD5392-31
AD5391-31
Unit
Test Conditions/Comments
0.4
DVDD − 0.5
DVDD − 0.1
±1
5
0.4
DVDD − 0.5
DVDD − 0.1
±1
5
V max
V min
V min
μA max
pF typ
DVDD = 2.7 V to 5.5 V, sinking 200 μA
DVDD = 2.7 V to 3.6 V, SDO only, sourcing 200 μA
DVDD = 4.5 V to 5.5 V, SDO only, sourcing 200 μA
0.4
0.6
±1
8
0.4
0.6
±1
8
V max
V max
μA max
pF typ
ISINK = 3 mA
ISINK = 6 mA
2.7/3.6
2.7/5.5
2.7/3.6
2.7/5.5
V min/max
V min/max
−85
0.375
−85
0.375
AIDD
0.475
0.475
DIDD
AIDD (Power-Down)
DIDD (Power-Down)
Power Dissipation
1
1
20
21
1
1
20
21
dB typ
mA/channel
max
mA/channel
max
mA max
μA max
μA max
mW max
12
12
mW max
Parameter
Logic Outputs (BUSY, SDO)2
Output Low Voltage
Output High Voltage
High Impedance Leakage Current
High Impedance Output
Capacitance
Logic Output (SDA)2
VOL, Output Low Voltage
Three-State Leakage Current
Three-State Output
Capacitance
POWER REQUIREMENTS
AVDD
DVDD
Power Supply Sensitivity2
∆Midscale/∆AVDD
AIDD
1
Outputs unloaded, boost off,
0.25 mA/channel typ
Outputs unloaded, boost on,
0.325 mA/channel typ
VIH = DVDD, VIL = DGND
AD5390/AD5391 with outputs unloaded,
AVDD = DVDD = 3 V, boost off
AD5392 with outputs unloaded,
AVDD = DVDD = 3 V, boost off
AD539x-3 products are calibrated with a 1.25 V reference. Temperature range for all versions: −40°C to +85°C.
Guaranteed by characterization, not production tested.
Programmable either to 1.25 V typical or 2.5 V typical via the AD539x control register. Operating the AD539x-3 products with a reference of 2.5 V leads to a
degradation in performance accuracy.
4
Accuracy guaranteed from VOUT = 39 mV to AVDD − 50 mV.
2
3
Rev. C | Page 8 of 40
AD5390/AD5391/AD5392
AD5390-3/AD5391-3/AD5392-3 AC CHARACTERISTICS
AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V; CL = 200 pF to AGND.
Table 5.
Parameter
DYNAMIC PERFORMANCE
Output Voltage Settling Time
AD5390/AD5392
AD5391
Slew Rate 2
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Channel-to-Channel Isolation
DAC-to-DAC Crosstalk
Digital Crosstalk
Digital Feedthrough
OUTPUT NOISE (0.1 Hz to 10 Hz)
Output Noise Spectral Density
@ 1 kHz
@ 10 kHz
1
2
All 1
Unit
Test Conditions/Comments
8
10
6
8
3
2
12
15
100
1
0.8
0.1
15
40
μs typ
μs max
μs typ
μs max
V/μs typ
V/μs typ
nV-s typ
mV typ
dB typ
nV-s typ
nV-s typ
nV-s typ
μV p-p typ
μV p-p typ
¼ scale to ¾ scale change settling to ±1 LSB
150
100
nV/(Hz)1/2 typ
nV/(Hz)1/2 typ
¼ scale to ¾ scale change settling to ±1 LSB
Boost mode on
Boost mode off
See the Terminology section
See the Terminology section
Effect of input bus activity on DAC output under test
External reference midscale loaded to DAC
Internal reference midscale loaded to DAC
Guaranteed by design and characterization, not production tested.
The slew rate can be programmed via the current boost control bit in the AD539x control registers.
Rev. C | Page 9 of 40
AD5390/AD5391/AD5392
TIMING CHARACTERISTICS
SERIAL SPI-, QSPI-, MICROWIRE-, AND DSP-COMPATIBLE INTERFACE
DVDD = 2 V to 5.5 V; AVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 6. 3-Wire Serial Interface 1
Parameter 2, 3
t1
t2
t3
t4
t5 4
t64
t7
t7
t8
t9
t104
t11
t124
t13
t14
t15
t16
t17
t17
t18
t19
t20 5
t214
t224
t234
Limit at TMIN, TMAX
33
13
13
13
13
33
10
50
5
4.5
30
670
20
20
100
0
100
8
6
20
12
20
5
8
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns max
ns min
ns min
μs typ
μs typ
ns min
μs max
ns max
ns min
ns min
ns min
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
24th SCLK falling edge to SYNC falling edge
Minimum SYNC low time
Minimum SYNC high time
Minimum SYNC high time in readback mode
Data setup time
Data hold time
24th SCLK falling edge to BUSY falling edge
BUSY pulse width low (single channel update)
24th SCLK falling edge to LDAC falling edge
LDAC pulse width low
BUSY rising edge to DAC output response time
BUSY rising edge to LDAC falling edge
LDAC falling edge to DAC output response time
DAC output settling time, AD5390/AD5392
DAC output settling time, AD5391
CLR pulse width low
CLR pulse activation time
SCLK rising edge to SDO valid
SCLK falling edge to SYNC rising edge
SYNC rising edge to SCLK rising edge
SYNC rising edge to LDAC falling edge
1
Guaranteed by design and characterization, not production tested.
All input signals are specified with tr = tf = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.2 V.
3
See Figure 2, Figure 3, Figure 4, and Figure 5.
4
Standalone mode only.
5
Daisy-chain mode only.
2
t1
SCLK
24
t3
t7
SYNC
t22
t21
t4
t8
DIN
48
t2
t9
DB23
DB0
DB23
DB0
INPUT WORD FOR DAC N
INPUT WORD FOR DAC N+1
t20
DB23
UNDEFINED
DB0
INPUT WORD FOR DAC N
t23
t13
LDAC
Figure 2. Serial Interface Timing Diagram (Daisy-Chain Mode)
Rev. C | Page 10 of 40
03773-002
SDO
AD5390/AD5391/AD5392
t1
SCLK
1
24
2
t3
t4
t7
SYNC
t2
t5
t6
t8
t9
DB23
DIN
24
DB0
t10
BUSY
t11
t12
t13
LDAC1
t17
t14
VOUT 1
t15
t13
LDAC2
t17
t16
VOUT 2
t18
CLR
t19
03773-005
VOUT
1LDAC ACTIVE DURING BUSY
2LDAC ACTIVE DURING BUSY
Figure 3. Serial Interface Timing Diagram (Standalone Mode)
SCLK
24
48
t7A
SYNC
DB0
DB23'
DB0
INPUT WORD SPECIFIES
REGISTER TO BE READ
NOP CONDITION
SDO
DB23
DB0
SELECTED REGISTER DATA
CLOCKED OUT
UNDEFINED
Figure 4. Serial Interface Timing Diagram (Data Readback Mode)
200µA
TO
OUTPUT
PIN
IOL
VOH (MIN) OR
VOL (MAX)
CL
50pF
200µA
IOH
Figure 5. Load Circuit for Digital Output Timing
Rev. C | Page 11 of 40
03773-006
DB23
03773-003
DIN
AD5390/AD5391/AD5392
I2C SERIAL INTERFACE
DVDD = 2.7 V to 5.5 V; AVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 7. I2C Serial Interface 1
Parameter 2
FSCL
t1
t2
t3
t4
t5
t6 3
t7
t8
t9
t10
t11
CB 4
Limit at TMIN, TMAX
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
300
0
300
20 + 0.1 CB
400
Unit
kHz max
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
Description
SCL clock frequency
SCL cycle time
tHIGH, SCL high time
tLOW, SCL low time
tHD, STA, start/repeated start condition hold time
tSU, DAT, data setup time
tHD, DAT data hold time
tHD, DAT data hold time
tSU, STA setup time for repeated start
tSU, STO stop condition setup time
tBUF, bus free time between a stop and a start condition
tF, fall time of SDA when transmitting
tR, rise time of SCL and SDA when receiving (CMOS-compatible)
tF, fall time of SDA when transmitting
tF, fall time of SDA when receiving (CMOS-compatible)
tF, fall time of SCL and SDA when receiving
tF, fall time of SCL and SDA when transmitting
Capacitive load for each bus line
1
Guaranteed by design and characterization, not production tested.
See Figure 6.
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH MIN of the SCL signal) to bridge the undefined region of SCL’s falling edge.
4
CB is the total capacitance of one bus line in pF; tR and tF measured between 0.3 DVDD and 0.7 DVDD.
2
3
SDA
t9
t3
t10
t11
t4
SCL
t6
t2
t5
t7
REPEATED
START
CONDITION
START
CONDITION
Figure 6. I2C Interface Timing Diagram
Rev. C | Page 12 of 40
t1
t8
STOP
CONDITION
03773-007
t4
AD5390/AD5391/AD5392
ABSOLUTE MAXIMUM RATINGS
Transient currents of up to 100 mA do not cause SCR latch-up.
TA = 25°C, unless otherwise noted.
Table 8.
Parameter
AVDD to AGND
DVDD to DGND
Digital Inputs to DGND
Digital Outputs to DGND
VREF to AGND
REFOUT to AGND
AGND to DGND
VOUTX to AGND
Operating Temperature Range
Commercial (B Version)
Storage Temperature Range
Junction Temperature (TJ max)
64-Lead LFCSP, θJA
52-Lead LQFP, θJA
Reflow Soldering Peak Temperature
Rating
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to DVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to +0.3 V
−0.3 V to AVDD + 0.3 V
Stresses above absolute maximum ratings may cause permanent
damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above
those listed in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
ESD CAUTION
−40°C to +85°C
−65°C to +150°C
150°C
22°C/W
38°C/W
230°C
Rev. C | Page 13 of 40
AD5390/AD5391/AD5392
NC
NC
NC
NC
NC
NC
REF_GND
REFOUT/REFIN
SIGNAL_GND 1
DAC_GND 1
AVDD 1
VOUT 0
VOUT 1
VOUT 2
VOUT 3
VOUT 4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLR
DGND
SYNC/AD0
DIN/SDA
SCLK/SCL
SDO
DVDD
DGND
DGND
DVDD
DVDD
DGND
SPI/I2C
PD
DCEN/AD1
LDAC
DGND
SYNC/AD0
DIN/SDA
SCLK/SCL
SDO
DVDD
DGND
DVDD
DVDD
DGND
SPI/I2C
PD
DCEN/AD1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PIN CONFIGURATON AND FUNCTION DESCRIPTIONS
52 51 50 49 48 47 46 45 44 43 42 41 40
PIN 1
INDICATOR
AD5390/
AD5391
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
CLR
NC
NC
REF_GND
REFOUT/REFIN
SIGNAL_GND 1
DAC_GND 1
AVDD 1
VOUT 0
VOUT 1
VOUT 2
VOUT 3
VOUT 4
NC
BUSY
RESET
NC
NC
NC
NC
NC
NC
NC
NC
AVDD 2
AGND 2
VOUT 15
VOUT 14
VOUT 13
1
2
3
39
38
PIN 1
INDICATOR
37
36
4
5
6
7
8
9
35
AD5390/
AD5391
34
33
TOP VIEW
(Not to Scale)
32
31
10
30
11
29
12
28
27
13
LDAC
BUSY
RESET
NC
NC
NC
NC
AVDD 2
AGND 2
VOUT 15
VOUT 14
VOUT 13
SIGNAL_GND 2
03773-008
Figure 9. AD5390/AD5391 LQFP Pin Configuration
DGND
SYNC/AD0
DIN/SDA
SCLK/SCL
SDO
DVDD
DGND
DVDD
DVDD
DGND
SPI/I2C
PD
DCEN/AD1
CLR
DGND
SYNC/AD0
DIN/SDA
SCLK/SCL
SDO
DVDD
DGND
DGND
DVDD
DVDD
DGND
SPI/I2C
PD
DCEN/AD1
LDAC
Figure 7. AD5390/AD5391 LFCSP Pin Configuration
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
52 51 50 49 48 47 46 45 44 43 42 41 40
AD5392
TOP VIEW
(Not to Scale)
NC
BUSY
RESET
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
39 LDAC
1
2
38 BUSY
PIN 1
INDICATOR
3
37 RESET
36 NC
4
35 NC
5
6
AD5392
34 NC
7
TOP VIEW
(Not to Scale)
32 NC
8
33 NC
9
31 NC
10
30 NC
11
29 NC
12
28 NC
13
27 SIGNAL_GND 2
Figure 10. AD5392 LQFP Pin Configuration
Figure 8. AD5392 LFCSP Pin Configuration
Rev. C | Page 14 of 40
03773-011
NC
DAC_GND 2
NC
03773-009
NC
NC = NO CONNECT
AGND 1
VOUT 5
VOUT 6
VOUT 7
MON_IN 1
MON_IN 2
MON_OUT
NC
NC
14 15 16 17 18 19 20 21 22 23 24 25 26
AGND 1
NC
NC
VOUT 5
VOUT 6
VOUT 7
MON_IN 1
MON_IN 2
MON_OUT
NC
NC
NC
NC
NC
DAC_GND 2
SIGNAL_GND 2
NC = NO CONNECT
PIN 1
INDICATOR
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
CLR
NC
NC
REF_GND
REFOUT/REFIN
SIGNAL_GND 1
DAC_GND 1
AVDD 1
VOUT 0
VOUT 1
VOUT 2
VOUT 3
VOUT 4
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NC 1
NC 2
NC 3
NC 4
NC 5
NC 6
REF_GND 7
REFOUT/REFIN 8
SIGNAL_GND 1 9
DAC_GND 1 10
AVDD 1 11
VOUT 0 12
VOUT 1 13
VOUT 2 14
VOUT 3 15
VOUT 4 16
03773-010
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NC = NO CONNECT
AGND 1
NC
NC
VOUT 5
VOUT 6
VOUT 7
MON_IN 1
MON_IN 2
MON_OUT
VOUT 8
VOUT 9
VOUT 10
VOUT 11
VOUT 12
DAC_GND 2
SIGNAL_GND 2
NC = NO CONNECT
AGND 1
VOUT 5
VOUT 6
VOUT 7
MON_IN 1
MON_IN 2
MON_OUT
VOUT 8
VOUT 9
VOUT 10
VOUT 11
VOUT 12
DAC_GND 2
14 15 16 17 18 19 20 21 22 23 24 25 26
AD5390/AD5391/AD5392
Table 9. Pin Function Descriptions
Mnemonic
VOUT X
SIGNAL_GND 1,
SIGNAL_GND 2
DAC_GND 1,
DAC_GND 2
AGND 1, AGND 2
AVDD 1, AVDD 2
DGND
DVDD
REF_GND
REFOUT/REFIN
MON_OUT
MON_IN 1,
MON_IN 2
SYNC/AD0
DCEN/AD1
SDO
BUSY
LDAC
CLR
RESET
Function
Buffered Analog Outputs for Channel X. Each analog output is driven by a rail-to-rail output amplifier operating at a gain
of 2. Each output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω.
Analog Ground Reference Points for each group of eight output channels. All SIGNAL_GND pins are tied together
internally and should be connected to the AGND plane as close as possible to the AD539x.
Each group of eight channels contains a DAC_GND pin. This is the ground reference point for the internal 14-bit DACs.
These pins should be connected to the AGND plane.
Analog Ground Reference Point. Each group of eight channels contains an AGND pin. All AGND pins should be
connected externally to the AGND plane.
Analog Supply Pins. Each group of eight channels has a separate AVDD pin. These pins should be decoupled with 0.1 uF
ceramic capacitors and 10 μF tantalum capacitors. Operating range is 5 V ± 10%.
Ground for All Digital Circuitry.
Logic Power Supply. Guaranteed operating range is 2.7 V to 5.5 V. Recommended that these pins be decoupled with
0.1 μF ceramic capacitors and 10 μF tantalum capacitors to DGND.
Ground Reference Point for the Internal Reference. Connect to AGND.
The AD539x contains a common REFOUT/REFIN pin. When the internal reference is selected, this pin is the reference
output. If the application necessitates the use of an external reference, it can be applied to this pin and the internal
reference disabled via the control register. The default for this pin is a reference input.
Analog Output Pin. When the monitor function is enabled on the AD5390/AD5391, the MON_OUT acts as the output of
a 16-to-1 channel multiplexer that can be programmed to multiplex any channel output to the MON_OUT pin. When the
monitor function is enabled on the AD5392, the MON_OUT acts as the output of an 8-to-1 channel multiplexer that can
be programmed to multiplex any channel output to the MON_OUT pin. The MON_OUT pin output impedance is
typically 500 Ω and is intended to drive a high input impedance such as that exhibited by SAR ADC inputs.
Monitor Input Pins. The AD539x contains two monitor input pins to which the user can connect input signals (within the
maximum ratings of the device) for monitoring purposes. Any of the signals applied to the MON_IN pins along with the
output channels can be switched to the MON_OUT pin via software. An external ADC, for example, can be used to
monitor these signals.
Serial Interface Pin. This is the frame synchronization input signal for the serial interface. When taken low, the internal
counter is enabled to count the required number of clocks before the addressed register is updated.
In I2C mode, AD0 acts as a hardware address pin.
Interface Control Pin. Operation is determined by the interface select bit SPI/I2C.
Serial Interface Mode: Daisy-Chain Select Input (level-sensitive, active high). When high, this pin enables daisy-chain
operation to allow a number of devices to be cascaded together.
I2C Mode: This pin acts as a hardware address pin used in conjunction with AD0 to determine the software address for
this device on the I2C bus.
Serial Data Output. Three-state CMOS output. SDO can be used for daisy-chaining a number of devices together. Data is
clocked out on SDO on the rising edge of SCLK and is valid on the falling edge of SCLK.
Digital CMOS Output. BUSY goes low during internal calculations of the data (x2) loaded to the DAC data register. During
this time, the user can continue writing new data to further the x1, c, and m registers (these are stored in a FIFO), but no
further updates to the DAC registers and DAC outputs can take place. If LDAC is taken low while BUSY is low, this event is
stored. BUSY also goes low during power-on reset and when the RESET pin is low. During this time the interface is
disabled and any events on LDAC are ignored. A CLR operation also brings BUSY low.
Load DAC Logic Input (active low). If LDAC is taken low while BUSY is inactive (high), the contents of the input registers
are transferred to the DAC registers and the DAC outputs are updated. If LDAC is taken low while BUSY is active and
internal calculations are taking place, the LDAC event is stored and the DAC registers are updated when BUSY goes
inactive. However, any events on LDAC during power-on reset or RESET are ignored.
Asynchronous Clear Input. The CLR input is falling edge sensitive. While CLR is low, all LDAC pulses are ignored. When
CLR is activated, all channels are updated with the data contained in the CLR code register. BUSY is low for a duration of
20 μs (AD5390/AD5391) and 15 μs (AD5392) while all channels are being updated with the CLR code.
Asynchronous Digital Reset Input (falling edge sensitive). The function of this pin is equivalent to that of the power-on
reset generator. When this pin is taken low, the state machine initiates a reset sequence to digitally reset the x1, m, c, and
x2 registers to their default power-on values. This sequence takes 270 μs maximum. This falling edge of RESET initiates
the RESET process and BUSY goes low for the duration, returning high when RESET is complete. While BUSY is low, all
interfaces are disabled and all LDAC pulses are ignored. When BUSY returns high, the part resumes normal operation
and the status of the RESET pin is ignored until the next falling edge is detected.
Rev. C | Page 15 of 40
AD5390/AD5391/AD5392
Mnemonic
PD
SPI/I2C
SCLK/SCL
DIN/SDA
Exposed Pad
(LFCSP only)
Function
Power-Down (level-sensitive, active high). Used to place the device in low power mode, in which the device consumes
1 μA analog current and 20 μA digital current. In power-down mode, all internal analog circuitry is placed in low power
mode; the analog output is configured as high impedance outputs or provides a 100 kΩ load to ground, depending on
how the power-down mode is configured. The serial interface remains active during power-down.
Interface Select Input Pin. When this input is low, I2C mode is selected. When this input is high, SPI mode is selected.
Interface Clock Input Pin. In SPI-compatible serial interface mode, this pin acts as a serial clock input. It operates at clock
speeds up to 50 MHz.
I2C mode: In I2C mode, this pin performs the SCL function, clocking data into the device. Data transfer rate in I2C mode is
compatible with both 100 kHz and 400 kHz operating modes.
Interface Data Input Pin.
SPI/I2C = 1: This pin acts as the serial data input. Data must be valid on the falling edge of SCLK.
SPI/I2C = 0, I2C mode: In I2C mode, this pin is the serial data pin (SDA) operating as an open drain input/output.
This pad should be connected to the ground plane.
Rev. C | Page 16 of 40
AD5390/AD5391/AD5392
TERMINOLOGY
Relative Accuracy or Endpoint Linearity (INL)
A measure of the maximum deviation from a straight line
passing through the endpoints of the DAC transfer function.
It is measured after adjusting for zero-scale error and full-scale
error and is expressed in least significant bits (LSBs).
Differential Nonlinearity (DNL)
The difference between the measured change and the ideal
1 LSB change between any two adjacent codes. A specified
differential nonlinearity of 1 LSB maximum ensures monotonicity.
DC Output Impedance
The effective output source resistance. It is dominated by
package lead resistance.
Output Voltage Settling Time
The amount of time it takes for the output of a DAC to settle
to a specified level for a ¼ to ¾ full-scale input change. It is
measured from the rising edge of BUSY.
Digital-to-Analog Glitch Energy
The amount of energy injected into the analog output at the
major code transition. It is specified as the area of the glitch in
nV-s. It is measured by toggling the DAC register data between
0x1FFF and 0x2000.
Zero-Scale Error
The error in the DAC output voltage when all 0s are loaded
into the DAC register. Ideally, with all 0s loaded to the DAC
and m = all 1s, c = 2n−1, VOUT(Zero-Scale) = 0 V.
Zero-scale error is a measure of the difference between VOUT
(actual) and VOUT (ideal) expressed in mV. It is mainly caused
by offsets in the output amplifier.
Offset Error
A measure of the difference between VOUT (actual) and VOUT
(ideal) expressed in mV in the linear region of the transfer
function. Offset error is measured on the AD539x-5 with code
32 loaded in the DAC register and with code 64 loaded in the
DAC register on the AD539x-3.
Gain Error
The deviation in slope of the DAC transfer characteristic from
ideal and is expressed in % FSR with the DAC output unloaded.
Gain error is specified in the linear region of the output range
between VOUT = 10 mV and VOUT = AVDD − 50 mV.
DC Crosstalk
The dc change in the output level of one DAC at midscale in
response to a full-scale code (all 0s to all 1s and vice versa) and
the output change of all other DACs. It is expressed in LSBs.
DAC-to-DAC Crosstalk
The glitch impulse that appears at the output of one DAC due to
both the digital change and subsequent analog output change at
another DAC. The victim channel is loaded with midscale, and
DAC-to-DAC crosstalk is specified in nV-s.
Digital Crosstalk
The glitch impulse transferred to the output of one converter
due to a change in the DAC register code of another converter
is defined as the digital crosstalk and is specified in nV-s.
Digital Feedthrough
When the device is not selected, high frequency logic activity
on the device’s digital inputs can be capacitively coupled both
across and through the device to show up as noise on the VOUT
pins. It can also be coupled along the supply and ground lines.
This noise is digital feedthrough.
Output Noise Spectral Density
This is a measure of internally generated random noise. Random
noise is characterized as a spectral density (voltage per √Hz).
It is measured by loading all DACs to midscale and measuring
noise at the output. It is measured in nV/(Hz)1/2 in a 1 Hz
bandwidth at 10 kHz.
Rev. C | Page 17 of 40
AD5390/AD5391/AD5392
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
1.00
AVDD = DVDD = 5.5V
VREF = 2.5V
TA = 25°C
1.5
0.75
0.5
0
–0.5
0.25
0
–0.25
–1.0
–0.50
–1.5
–0.75
–2.0
0
4096
8192
INPUT CODE
12288
16384
–1.00
03773-043
INL ERROR (LSB)
0.50
03773-040
0
3072
3584
4096
3584
4096
0
–0.5
0.25
0
–0.25
–0.50
–1.5
–0.75
0
4096
8192
INPUT CODE
12288
16384
03773-041
–1.0
–1.00
1024
1536
2048
2560
3072
40
AVDD = 5V
REFOUT = 2.5V
35 TEMP. RANGE = 25°C TO 85°C
SAMPLE SIZE = 162
30
FREQUENCY
10
8
6
4
25
20
15
10
2
0
512
Figure 15. Typical AD5391-3 INL Plot
AVDD = 5.5V
REFIN = 2.5V
TA = 25°C
12
0
INPUT CODE
Figure 12. AD5390-3/AD5392-3 INL Plot
14
03773-044
INL ERROR (LSB)
0.50
5
03773-042
INL ERROR (LSB)
2560
0.75
0.5
NUMBER OF UNITS
2048
1.00
1.0
–2.0
1536
Figure 14. Typical AD5391-5 INL Plot
AVDD = DVDD = 3V
VREF = 1.25V
TA = 25°C
1.5
1024
INPUT CODE
Figure 11. AD5390-5/AD5392-5 Typical INL Plot
2.0
512
–2
–1
0
1
0
–5.0 –4.0 –3.0 –2.0 –1.0
0
1.0 2.0 3.0 4.0 5.0
–4.5 –3.5 –2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 4.5
REFERENCE DRIFT (ppm/°C)
2
INL ERROR DISTRIBUTION (LSB)
Figure 13. AD5390/AD5392 INL Histogram Plot
Figure 16. AD539x REFOUT Temperature Coefficient
Rev. C | Page 18 of 40
03773-045
INL ERROR (LSB)
1.0
AD5390/AD5391/AD5392
6
FULL SCALE
WR
5
BUSY
4
MIDSCALE
3
VOUT (V)
AVDD = DVDD = 5V
VREF = 2.5V
TA = 25°C
EXITS SOFT PD
TO MIDSCALE
2
VOUT
AVDD = DVDD = 5V
VREF = 2.5V
TA = 25°C
3/4 SCALE
1/4 SCALE
1
ZERO SCALE
–1
–40
–20
–10
–5
–2
0
2
CURRENT (mA)
5
10
20
40
03773-049
03773-046
0
Figure 20. AD539x-5 Source and Sink Capability
Figure 17. AD539x Exiting Soft Power-Down
0.20
PD
AVDD = 5V
VREF = 2.5V
TA = 25°C
0.15
ERROR VOLTAGE (V)
0.10
AVDD = DVDD = 5V
VREF = 2.5V
TA = 25°C
EXITS HARDWARE PD
TO MIDSCALE
0
–0.05
(VDD–VOUT) AT FULL-SCALE SOURCING CURRENT
–0.10
–0.20
0
0.25
0.50
0.75
1.00
1.25
ISOURCE /ISINK (mA)
1.50
1.75
2.00
03773-050
–0.15
03773-047
Figure 21. Headroom at Rails vs. Source/Sink Current
Figure 18. AD539x Exiting Hardware Power-Down
AVDD = DVDD = 5V
VREF = 2.5V
TA = 25°C
POWER SUPPLY RAMP RATE = 10ms
AMPLITUDE (V)
VOUT
03773-048
AVDD
2.539
2.538
2.537
2.536
2.535
2.534
2.533
2.532
2.531
2.530
2.529
2.528
2.527
2.526
2.525
2.524
2.523
Figure 19. AD539x Power-Up Transient
AVDD = DVDD = 5V
VREF = 2.5V
TA = 25°C
14ns/SAMPLE NUMBER
1 LSB CHANGE AROUND MIDSCALE
GLITCH IMPULSE = 10nV-s
0
50
100
150
200 250 300 350
SAMPLE NUMBER
400
450
Figure 22. AD539x-5 Glitch Impulse Energy
Rev. C | Page 19 of 40
500
550
03773-051
VOUT
ERROR AT ZERO SINKING CURRENT
0.05
AD5390/AD5391/AD5392
1.254
AVDD = DVDD = 3V
VREF = 1.25V
TA = 25°C
14ns/SAMPLE NUMBER
1 LSB CHANGE AROUND MIDSCALE
GLITCH IMPULSE = 5nV-s
1.252
1.250
1.249
1.248
8
6
4
1.247
03773-055
2
1.246
0
50
100
150
200 250 300 350
SAMPLE NUMBER
400
450
500
550
0
03773-052
1.245
0.4
0.5
0.6
0.7
0.8
0.9
DIDD (mA)
Figure 26. AD539x DIDD Histogram
Figure 23. AD539x-3 Glitch Impulse
2.456
AVDD = DVDD = 5V
VREF = 2.5V
TA = 25°C
14ns/SAMPLE NUMBER
2.455
AVDD = DVDD = 5V
VREF = 2.5V
TA = 25°C
AMPLITUDE (V)
2.454
VOUT
2.453
2.452
2.451
2.449
0
50
100
150
200 250 300 350
SAMPLE NUMBER
450
500
550
Figure 27. AD539x Adjacent Channel Crosstalk
Figure 24. AD539x Slew Rate Boost Off
600
AVDD = 5V
TA = 25°C
REFOUT DECOUPLED
WITH 100nF CAPACITOR
VOUT
400
300
100
03773-054
REFOUT = 2.5V
200
0
100
REFOUT = 1.25V
1k
10k
FREQUENCY (Hz)
Figure 25. AD539x Slew Rate Boost On
Figure 28. AD539x REFOUT Noise Spectral Density
Rev. C | Page 20 of 40
100k
03773-057
OUTPUT NOISE (nV/ Hz)
500
AVDD = DVDD = 5V
VREF = 2.5V
TA = 25°C
400
03773-056
2.450
03773-053
AMPLITUDE (V)
1.251
DVDD = 5.5V
VIH = DVDD
VIL = DGND
TA = 25°C
10
NUMBER OF UNITS
1.253
AD5390/AD5391/AD5392
6
AVDD = DVDD = 5V
TA = 25°C
DAC LOADED WITH MIDSCALE
EXTERNAL REFERENCE
Y AXIS = 5µV/DIV
X AXIS = 100ms/DIV
5
AVDD = DVDD = 3V
VREF = 1.25V
TA = 25°C
VOUT (V)
4
3
3/4 SCALE
FULL SCALE
MIDSCALE
2
1
ZERO SCALE
–1
–40
Figure 29. 0.1 Hz to 10 Hz Output Noise Plot
–20
–10
–5
1/4 SCALE
–2
0
2
CURRENT (mA)
5
10
20
40
Figure 30. AD539x-3 Source and Sink Current Capability
Rev. C | Page 21 of 40
03773-059
03773-058
0
AD5390/AD5391/AD5392
FUNCTIONAL DESCRIPTION
DAC ARCHITECTURE
The AD5390/AD5391 are complete single-supply, 16-channel,
voltage output DACs offering a resolution of 14 bits and 12 bits,
respectively. The AD5392 is a complete single-supply, 8-channel,
voltage output DAC offering 14-bit resolution. All devices are
available in a 64-lead LFCSP and 52-lead LQFP, and feature
serial interfaces. This family includes an internal select-able
1.25 V/2.5 V, 10 ppm/°C reference that can be used to drive the
buffered reference inputs (alternatively, an external reference
can be used to drive these inputs). All channels have an on-chip
output amplifier with rail-to-rail output capable of driving a
5 kΩ load in parallel with a 200 pF capacitance.
The architecture of a single DAC channel consists of a 12-bit
and 14-bit resistor-string DAC followed by an output buffer
amplifier operating at a gain of 2. This resistor-string architecture
guarantees DAC monotonicity. The 12-bit and 14-bit binary
digital code loaded to the DAC register determines at what
node on the string the voltage is tapped off before being fed to
the output amplifier. Each channel on these devices contains
independent offset and gain control registers, allowing the user
to digitally trim offset and gain.
VREF
AVDD
x1 INPUT
REG
m REG
x2
DAC
REG
14-BIT
DAC
c REG
x 2 = ((m + 2 ) / 2n )× x1 + (c − 2n −1 )
where:
x2 is the data-word loaded to the resistor-string DAC.
x1 is the 12-bit and 14-bit data-word written to the DAC input
register.
m is the 12-bit and 14-bit gain coefficient (default is all 0x3FFE
on the AD5390/AD5392 and 0xFFE on the AD5391). The LSB
of the gain coefficient is zero.
n = DAC resolution (n = 14 for the AD5390/AD5392 and
n = 12 for the AD5391).
c is the 12-bit and 14-bit offset coefficient (default is 0x2000 on
the AD5390/AD5392 and 0x800 on the AD5391).
The complete transfer function for these devices can be
represented as
VOUT = 2 × VREF × x 2 / 2n
where:
x2 is the data-word loaded to the resistor-string DAC.
VREF is the reference voltage applied to the REFIN/REFOUT pin
on the DAC when an external reference is used (2.5 V for specified
performance on the AD539x-5 products and 1.25 V on the
AD539x-3 products).
VOUT
R
R
03773-018
INPUT
DATA
The digital input transfer function for each DAC can be
represented as
Figure 31. Single-Channel Architecture
These registers let the user calibrate out errors in the complete
signal chain including the DAC using the internal m and c
registers, which hold the correction factors. All channels are
double-buffered, allowing synchronous updating of all channels
using the LDAC pin. Figure 31 shows a block diagram of a
single channel on the AD5390/AD5391/AD5392.
Rev. C | Page 22 of 40
AD5390/AD5391/AD5392
DATA DECODING
AD5391
AD5390/AD5392
The AD5391 contains an internal 12-bit data bus. The input
data is decoded depending on the value loaded to the REG1 and
REG0 bits of the input serial register. The input data from the
serial input register is loaded into the addressed DAC input
register, offset (c) register, or gain (m) register. The format data
and the offset (c) and gain (m) register contents are shown in
Table 14 to Table 16.
The AD5390/AD5392 contain an internal 14-bit data bus.
The input data is decoded depending on the data loaded to
the REG1 and REG0 bits of the input serial register. This is
shown in Table 10.
Data from the serial input register is loaded into the addressed
DAC input register, offset (c) register, or gain (m) register. The
format data, and the offset (c) and gain (m) register contents
are shown in Table 11 to Table 13.
Table 10. Register Selection
REG1
1
1
0
0
REG0
1
0
1
0
Register Selected
Input data register (x1)
Offset register (c)
Gain register (m)
Special function registers (SFRs)
Table 11. AD5390/AD5392 DAC Data Format
(REG1 = 1, REG0 = 1)
DB13 to DB0
11 1111
1111
11 1111
1111
10 0000
0000
10 0000
0000
01 1111
1111
00 0000
0000
00 0000
0000
1111
1110
0001
0000
1111
0001
0000
DB13 to DB0
111111
1111
111111
1111
100000
0000
100000
0000
011111
1111
000000
0000
000000
0000
1111
1110
0001
0000
1111
0001
0000
Offset (LSB)
+8191
+8190
+1
+0
–1
–8191
–8192
DB11 to DB0
1111
1111
1111
1111
1000
0000
1000
0000
0111
1111
0000
0000
0000
0000
DB11 to DB0
1111
1111
1111
1111
1000
0000
1000
0000
0111
1111
0000
0000
0000
0000
1110
1110
1110
1110
0000
1111
1110
0001
0000
1111
0001
0000
Offset (LSB)
+2047
+2046
+1
+0
–1
–2047
–2048
Table 16. AD5391 Gain Data Format (REG1 = 0, REG0 = 1)
DB11 to DB0
1111
1111
1011
1111
0111
1111
0011
1111
0000
0000
Table 13. AD5390/AD5392 Gain Data Format
(REG1 = 0, REG0 = 1)
DB13 to DB0
11 1111
1111
10 1111
1111
01 1111
1111
00 1111
1111
00 0000
0000
1111
1110
0001
0000
1111
0001
0000
DAC Output (V)
2 VREF × (4095/4096)
2 VREF × (4094/4096)
2 VREF × (2049/4096)
2 VREF × (2048/4096)
2 VREF × (2047/4096)
2 VREF × (1/4096)
0
Table 15. AD5391 Offset Data Format (REG1 = 1, REG0 = 0)
DAC Output (V)
2 VREF × (16383/16384)
2 VREF × (16382/16384)
2 VREF × (8193/16384)
2 VREF × (8192/16384)
2 VREF × (8191/16384)
2 VREF × (1/16384)
0
Table 12. AD5390/AD5392 Offset Data Format
(REG1 = 1, REG0 = 0)
Table 14. AD5391 DAC Data Format (REG1 = 1, REG0 = 1)
Gain Factor
1
0.75
0.5
0.25
0
Rev. C | Page 23 of 40
1110
1110
1110
1110
0000
Gain Factor
1
0.75
0.5
0.25
0
AD5390/AD5391/AD5392
INTERFACES
The AD5390/AD5391/AD5392 contain a serial interface that
can be programmed to be DSP-, SPI-, and MICROWIREcompatible, or I2C-compatible. The SPI/I2C pin is used to select
the interface mode.
Logic 1 pin to configure this mode of operation. The serial
interface control pins are described in Table 17.
Table 17. Serial Interface Control Pins
Pin
SYNC, DIN, SCLK
DCEN
SDO
To minimize both the power consumption of the device and the
on-chip digital noise, the interface fully powers up only when the
device is being written to, that is, on the falling edge of SYNC.
Description
Standard 3-wire interface pins.
Selects standalone mode or daisy-chain mode.
Data out pin for daisy-chain mode.
DSP-, SPI-, AND MICROWIRE-COMPATIBLE SERIAL
INTERFACE
Figure 2 to Figure 4 show timing diagrams for a serial write to
the AD5390/AD5391/AD5392 in both standalone and daisychain mode. The 24-bit data-word format for the serial interface
is shown in Table 18 to Table 20. Descriptions of the bits follow
in Table 21.
The serial interface can be operated with a minimum of three
wires in standalone mode or four wires in daisy-chain mode.
Daisy-chaining allows many devices to be cascaded together to
increase system channel count. The SPI/I2C pin is tied to a
Table 18. AD5390 16-Channel, 14-Bit DAC Serial Input Register Configuration
MSB
A/B
LSB
R/W
0
0
A3
A2
A1
A0
REG1
REG0
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB1 DB0
Table 19. AD5391 16-Channel, 12-Bit DAC Serial Input Register Configuration
MSB
A/B
LSB
R/W 0
0
A3 A2 A1
A0
REG1
REG0
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB7
DB6
DB5
DB4
X
X
Table 20. AD5392 8-Channel, 14-Bit DAC Serial Input Register Configuration
MSB
A/B
LSB
R/W 0
0
0
A2
A1
A0
REG1
REG0
DB13
DB12
DB11
DB10
DB9
DB8
DB3
DB2
DB1
DB0
Table 21. Serial Input Register Configuration Bit Descriptions
Bit
A/B
R/W
A3 to A0
REG1 and
REG0
DB13 to
DB0
X
Description
When toggle mode is enabled, this bit selects whether the data write is to the A or B register. With toggle mode disabled, this
bit should be set to zero to select the A data register.
The read or write control bit.
Used to address the input channels.
Select the register to which data is written, as outlined in Table 10.
Contain the input data-word.
Don’t care condition.
Rev. C | Page 24 of 40
AD5390/AD5391/AD5392
Standalone Mode
By connecting the daisy-chain enable (DCEN) pin low, standalone mode is enabled. The serial interface works with both a
continuous and a noncontinuous serial clock. The first falling
edge of SYNC starts the write cycle and resets a counter that
counts the number of serial clocks to ensure that the correct
number of bits is shifted into the serial shift register. Any
further edges on SYNC (except for a falling edge) are ignored
until 24 bits are clocked in. Once 24 bits have been shifted in,
the SCLK is ignored. For another serial transfer to take place,
the counter must be reset by the falling edge of SYNC.
Daisy-Chain Mode
For systems that contain several devices, the SDO pin can be
used to daisy-chain the devices together. This daisy-chain mode
can be useful in system diagnostics and for reducing the number
of serial interface lines.
By connecting the DCEN pin high, daisy-chain mode is
enabled. The first falling edge of SYNC starts the write cycle.
The SCLK is continuously applied to the input shift register
when SYNC is low. If more than 24 clock pulses are applied,
the data ripples out of the shift register and appears on the
SDO line. This data is clocked out on the rising edge of SCLK
and is valid on the falling edge. By connecting the SDO of the
first device to the DIN input on the next device in the chain,
a multidevice interface is constructed. For each device in the
system, 24 clock pulses are required. Therefore, the total
number of clock cycles must equal 24N where N is the total
number of AD539x devices in the chain.
When the serial transfer to all devices is complete, SYNC is
taken high. This latches the input data in each device in the
daisy chain and prevents any further data from being clocked
into the input shift register.
The serial clock can be either a continuous or a gated clock. A
continuous SCLK source can be used only if the SYNC can be
held low for the correct number of clock cycles. In gated clock
mode, a burst clock containing the exact number of clock cycles
must be used and SYNC taken high after the final clock to latch
the data.
Readback Mode
Readback mode is invoked by setting the R/W bit = 1 in the serial
input register write sequence. With R/W = 1, Bit A3 to Bit A0
in association with Bits REG1 and REG0 select the register to
be read. The remaining data bits in the write sequence are don’t
care bits. During the next SPI write, the data appearing on the
SDO output contains the data from the previously addressed
register. For a read of a single register, the NOP command can be
used in clocking out the data from the selected register on SDO.
The readback diagram in Figure 32 shows the readback sequence.
For example, to read back the m register of Channel 0 on the
AD539x, the following sequence should be implemented:
First, write 0x404XXX to the AD539x input register. This
configures the AD539x for read mode with the m register of
Channel 0 selected. Note that all data bits, DB13 to DB0, are
don’t care bits.
Follow this with a second write, a NOP condition, and 0x000000.
During this write, the data from the m register is clocked out on
the DOUT line, that is, data clocked out contains the data from
the m register in Bit DB13 to Bit DB0, and the top 10 bits contain the address information as previously written. In readback
mode, the SYNC signal must frame the data. Data is clocked out
on the rising edge of SCLK and is valid on the falling edge of
the SCLK signal. If the SCLK idles high between the write and
read operations of a readback, the first bit of data is clocked out
on the falling edge of SYNC.
If SYNC is taken high before 24 clocks are clocked into the part,
it is considered a bad frame and the data is discarded.
SCLK
24
48
SYNC
DB23
DB0
DB23
INPUT WORD SPECIFIES REGISTER TO BE READ
SDO
DB23
DB0
UNDEFINED
DB0
NOP CONDITION
DB23
SELECTED REGISTER DATA CLOCKED OUT
Figure 32. Readback Operation
Rev. C | Page 25 of 40
DB0
03773-022
DIN
AD5390/AD5391/AD5392
I2C SERIAL INTERFACE
Repeated START Condition
The AD5390/AD5391/AD5392 feature an I2C-compatible
2-wire interface consisting of a serial data line (SDA) and a
serial clock line (SCL). SDA and SCL facilitate communication
between the DACs and the master at rates up to 400 kHz.
Figure 6 shows the 2-wire interface timing diagram.
A repeated START (Sr) condition may indicate a change of data
direction on the bus. Sr may be used when the bus master is
writing to several I2C devices and does not want to relinquish
control of the bus.
When selecting the I2C operating mode by configuring the
SPI/I2C pin to Logic 0, the device is connected to the I2C bus
as a slave device, that is, no clock is generated by the device.
The AD5390/AD5391/AD5392 have a 7-bit slave address 1010 1
(AD1)(AD0). The five MSBs are hard-coded and the two LSBs
are determined by the state of the AD1 and AD0 pins. The
hardware configuration facility for the AD1 and AD0 pins
allows four of these devices to be configured on the bus.
The acknowledge bit (ACK) is the ninth bit attached to any 8-bit
data-word. An ACK is always generated by the receiving device.
The AD539x devices generate an ACK when receiving an address
or data by pulling SDA low during the ninth clock period.
I2C Data Transfer
One data bit is transferred during each SCL clock cycle. The
data on SDA must remain stable during the high period of the
SCL clock pulse. Changes in SDA while SCL is high are control
signals that configure START and STOP conditions. Both SDA
and SCL are pulled high by the external pull-up resistors when
the I2C bus is not busy.
START and STOP Conditions
A master device initiates communication by issuing a START
condition. A START condition is a high-to-low transition on
SDA with SCL high. A STOP condition is a low-to-high transition on SDA, while SCL is high. A START condition from the
master signals the beginning of a transmission to the AD539x.
The STOP condition frees the bus. If a repeated START
condition (Sr) is generated instead of a STOP condition, the
bus remains active.
Acknowledge Bit (ACK)
Monitoring the ACK allows for detection of unsuccessful data
transfers. An unsuccessful data transfer occurs if a receiving
device is busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master should reattempt
communication.
AD539X Slave Addresses
A bus master initiates communication with a slave device by
issuing a START condition followed by the 7-bit slave address.
When idle, the AD539x device waits for a START condition
followed by its slave address. The LSB of the address word is
the read/write (R/W) bit. The AD539x devices are receive
devices only and R/W = 0 when communicating with them.
After receiving the proper address 1010 1(AD1) (AD0), the
AD539x issues an ACK by pulling SDA low for one clock cycle.
The AD539x has four user-programmable addresses determined
by the AD1 and AD0 bits.
Rev. C | Page 26 of 40
AD5390/AD5391/AD5392
I2C WRITE OPERATION
There are three specific modes in which data can be written to
the AD539x family of DACs.
DAC to be addressed and is also acknowledged by the DAC.
Address Bits A3 to A0 address all channels on the AD5390/
AD5391. Address Bits A2 to A0 address all channels on the
AD5392. Address Bit A3 is a zero on the AD5392. Two bytes
of data are then written to the DAC, as shown in Figure 33.
A STOP condition follows. This lets the user update a single
channel within the AD539x at any time and requires four bytes
of data to be transferred from the master.
4-BYTE MODE
When writing to the AD539x DACs, begin with an address byte
(R/W = 0), after which the DAC acknowledges that it is prepared
to receive data by pulling SDA low. The address byte is followed
by the pointer byte. This addresses the specific channel in the
SCL
1
SDA
0
1
0
START
CONDITION
BY
MASTER
AD1
1
AD0
R/W
0
A/B
0
MSB
ACK
BY
CONVERTER
ADDRESS BYTE
0
A3
A2
A1
A0
ACK
BY
CONVERTER
POINTER BYTE
SCL
REG0
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
ACK
BY
CONVERTER
MOST SIGNIFICANT DATA BYTE
DB5
DB4
DB3
DB2
DB1
DB0
STOP
ACK
CONDITION
BY
BY
CONVERTER
MASTER
LEAST SIGNIFICANT DATA BYTE
Figure 33. AD5390/AD5392 4-Byte Mode I2C Write Operation
SCL
SDA
1
0
1
START
CONDITION
BY
MASTER
0
1
AD1
AD0
R/W
A/B
0
MSB
ACK
BY
CONVERTER
ADDRESS BYTE
0
0
A3
A2
A1
A0
ACK
BY
CONVERTER
POINTER BYTE
SCL
REG1
REG0
DB11
DB10
DB9
DB8
DB7
MOST SIGNIFICANT DATA BYTE
DB6
DB5
DB4
ACK
BY
CONVERTER
DB3
DB2
DB0
LEAST SIGNIFICANT DATA BYTE
Figure 34. AD5391 4-Byte Mode I2C Write Operation
Rev. C | Page 27 of 40
DB1
0
0
STOP
ACK
CONDITION
BY
BY
CONVERTER
MASTER
03773-021
SDA
03773-023
REG1
SDA
AD5390/AD5391/AD5392
3-BYTE MODE
on the AD5392. Address Bit A3 is a zero on the AD5392. This is
then followed by the two data bytes. REG1 and REG0 determine
the register to be updated.
The 3-byte mode lets the user update more than one channel in
a write sequence without having to write the device address byte
each time. The device address byte is required only once and
subsequent channel updates require the pointer byte and the
data bytes. In 3-byte mode, the user begins with an address byte
(R/W = 0) after which the DAC acknowledges that it is prepared
to receive data by pulling SDA low. The address byte is followed
by the pointer byte; this addresses the specific channel in the
DAC to be addressed and is also acknowledged by the DAC.
Address Bits A3 to A0 address all channels on the
AD5390/AD5391. Address Bits A2 to A0 address all channels
If a STOP condition is not sent following the data bytes,
another channel can be updated by sending a new pointer
byte followed by the data bytes. This mode requires only three
bytes to be sent to update any channel once the device has
been initially addressed and reduces the software overhead in
updating the AD539x channels. A STOP condition at any time
exits this mode. Figure 35 shows a typical configuration.
SCL
SDA
1
0
1
0
START
CONDITION
BY
MASTER
1
AD1
AD0
R/W
A/B
0
ACK
MSB
BY
CONVERTER
ADDRESS BYTE
0
0
A3
A2
A1
POINTER BYTE FOR CHANNEL N
A0
ACK
BY
CONVERTER
SCL
SDA
REG1
REG0
MSB
LSB
MSB
ACK
BY
CONVERTER
MOST SIGNIFICANT DATA BYTE
LSB
LEAST SIGNIFICANT DATA BYTE
ACK
BY
CONVERTER
DATA FOR CHANNEL N
SCL
SDA
0
0
0
0
A3
A2
A1
A0
MSB
POINTER BYTE FOR CHANNEL NEXT CHANNEL
ACK
BY
CONVERTER
SCL
REG1
REG0
MSB
LSB
MOST SIGNIFICANT DATA BYTE
MSB
ACK
BY
CONVERTER
LSB
LEAST SIGNIFICANT DATA BYTE
DATA FOR CHANNEL NEXT CHANNEL
Figure 35. 3-Byte Mode I2C Write Operation
Rev. C | Page 28 of 40
ACK
STOP
BY
CONDITION
CONVERTER
BY
MASTER
03773-024
SDA
AD5390/AD5391/AD5392
2-BYTE MODE
The REG0 and REG1 bits in the data byte determine the register
to be updated. In this mode, following the initialization, only
the two data bytes are required to update a channel. The
channel address automatically increments from Address 0 to
the final address and then returns to the normal 3-byte mode
of operation. This mode allows transmission of data to all
channels in one block and reduces the software overhead in
configuring all channels. A STOP condition at any time exits
this mode. Toggle mode of operation is not supported in
2-byte mode. Figure 36 shows a typical configuration.
The 2-byte mode lets the user update channels sequentially
following initialization of this mode. The device address byte is
required only once and the address pointer is configured for
autoincrement or burst mode.
The user must begin with an address byte (R/W = 0), after
which the DAC acknowledges that it is prepared to receive data
by pulling SDA low. The address byte is followed by a specific
pointer byte (0xFF), which initiates the burst mode of operation. The address pointer initializes to Channel 0 and the data
following the pointer is loaded to Channel 0. The address
pointer automatically increments to the next address.
SCL
1
SDA
0
1
START
CONDITION
BY
MASTER
0
1
AD1
AD0
R/W
A7 = 1 A6 = 1 A5 = 1 A4 = 1 A3 = 1 A2 = 1 A1 = 1 A0 = 1
MSB
ACK
BY
CONVERTER
ADDRESS BYTE
POINTER BYTE
ACK
BY
CONVERTER
SCL
SDA
REG1
REG0
MSB
LSB
MSB
LSB
ACK
BY
CONVERTER
MOST SIGNIFICANT DATA BYTE
LEAST SIGNIFICANT DATA BYTE
ACK
BY
CONVERTER
CHANNEL 0 DATA
SCL
SDA
REG1
REG0
MSB
LSB
MSB
LSB
ACK
BY
CONVERTER
MOST SIGNIFICANT DATA BYTE
LEAST SIGNIFICANT DATA BYTE
ACK
BY
CONVERTER
CHANNEL 1 DATA
SCL
REG1
REG0
MSB
LSB
MOST SIGNIFICANT DATA BYTE
MSB
ACK
BY
CONVERTER
LSB
LEAST SIGNIFICANT DATA BYTE
CHANNEL N DATA FOLLOWED BY STOP
Figure 36. 2-Byte Mode I2C Write Operation
Rev. C | Page 29 of 40
ACK
BY
CONVERTER
STOP
CONDITION
BY
MASTER
03773-025
SDA
AD5390/AD5391/AD5392
AD539x ON-CHIP SPECIAL FUNCTION REGISTERS
The AD539x family of parts contains a number of special
function registers (SFRs) as shown in Table 22. SFRs are
addressed with REG1 = 0 and REG0 = 0 and are decoded
using Address Bit A3 to Bit A0.
Table 22. SFR Register Functions (REG1 = 0, REG0 = 0)
R/ W
A3
A2
A1
A0
Function
X
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
0
1
0
0
1
0
0
0
0
1
1
0
1
0
0
1
0
0
0
1
NOP (no operation)
Write CLR code
Soft CLR
Soft power-down
Soft power-up
Control register write
Control register read
Monitor channel
Soft reset
Soft Power-Down
REG1 = REG0 = 0, A3 to A0 = 1000
DB13 to DB0 = Don’t Care
Executing this instruction performs a global power-down,
which puts all channels into a low power mode, reducing analog
current to 1 μA maximum and digital power consumption to
20 μA maximum. In power-down mode, the output amplifier
can be configured as a high impedance output or can provide a
100 kΩ load to ground. The contents of all internal registers are
retained in power-down mode.
Soft Power-Up
REG1 = REG0 = 0, A3 to A0 =1001
DB13 to DB0 = Don’t Care
This instruction is used to power up the output amplifiers and
the internal references. The time to exit power-down mode is
8 μs. The hardware power-down and software functions are
internally combined in a digital OR function.
Soft Reset
REG1 = REG0 = 0, A5 to A0 = 001111
DB13 to DB0 = Don’t Care
SFR Commands
NOP (No Operation)
REG1 = REG0 = 0, A3 to A0 = 0000
Performs no operation, but is useful in readback mode to clock
out data on SDO for diagnostic purposes. BUSY outputs a low
during a NOP operation.
Write CLR Code
REG1 = REG0 = 0, A3 to A0 = 0001
DB13 to DB0 = Contain the CLR data
Bringing the CLR line low or exercising the soft clear function
loads the contents of the DAC registers with the data contained
in the user-configurable CLR register and sets VOUT 0 to
VOUT 15, accordingly. This can be very useful not only for
setting up a specific output voltage in a clear condition but for
calibration purposes. For calibration, the user can load full scale
or zero scale to the clear code register and then issue a hardware
or software clear to load this code to all DACs, removing the
need for individual writes to all DACs. Default on power-up
is all zeros.
Soft CLR
REG1 = REG0 = 0, A3 to A0 = 0010
DB13 to DB0 = Don’t Care
Executing this instruction performs the CLR, which is
functionally the same as that provided by the external CLR pin.
The DAC outputs are loaded with the data in the CLR code
register. The time taken to execute fully the SOFT CLR is
20 μs on the AD5390/AD5391 and 15 μs on the AD5392. It
is indicated by the BUSY low time.
This instruction is used to implement a software reset. All
internal registers are reset to their default values, which
correspond to m at full scale and c at zero scale. The contents
of the DAC registers are cleared, setting all analog outputs to
0 V. The soft reset activation time is 135 μs maximum.
Monitor Channel
REG1 = REG0 = 0, A3 to A0 = 01010
DB13 to DB8 = Contain data to address the channel to be
monitored
A monitor function is provided on all devices. This feature,
consisting of a multiplexer addressed via the interface, allows
any channel output to be routed to the MON_OUT pin for
monitoring using an external ADC. In addition to monitoring
all output channels, two external inputs are also provided,
allowing the user to monitor signals external to the AD539x.
The channel monitor function must be enabled in the control
register before any channels are routed to the MON_OUT pin.
On the AD5390 and AD5392 14-bit parts, DB13 to DB8 contain
the channel address for the monitored channel. On the AD5391
12-bit part, DB11 to DB6 contain the channel address for the
channel to be monitored. Selecting Address 63 three-states the
MON_OUT pin.
The channel monitor decoding for the AD5390/AD5392 is
shown in Table 23 and the monitor decoding for the AD5391 is
shown in Table 24.
Rev. C | Page 30 of 40
AD5390/AD5391/AD5392
Table 23. AD5390/AD5392 Channel Monitor Decoding
REG1
REG0
A3
A2
A1
A0
DB13
DB12
DB11
DB10
DB9
DB8
DB7 to DB0
MON_OUT
(AD5390)
MON_OUT
(AD5392)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
VOUT 0
VOUT 1
VOUT 2
VOUT 3
VOUT 4
VOUT 5
VOUT 6
VOUT 7
VOUT 8
VOUT 9
VOUT 10
VOUT 11
VOUT 12
VOUT 13
VOUT 14
VOUT 15
MON_IN 1
MON_IN 2
Three-state
VOUT 0
VOUT 1
VOUT 2
VOUT 3
VOUT 4
VOUT 5
VOUT 6
VOUT 7
DB9
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
.
1
1
DB8
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
.
1
1
DB7
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
.
1
1
MON_IN 1
MON_IN 2
Three-state
Table 24. AD5391 Channel Monitor Decoding
REG1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
REG0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DB11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
DB10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
Rev. C | Page 31 of 40
DB6
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
.
0
1
DB5 to DB0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MON_OUT
(AD5391)
VOUT 0
VOUT 1
VOUT 2
VOUT 3
VOUT 4
VOUT 5
VOUT 6
VOUT 7
VOUT 8
VOUT 9
VOUT 10
VOUT 11
VOUT 12
VOUT 13
VOUT 14
VOUT 15
MON_IN 1
MON_IN 2
Undefined
Undefined
Undefined
Three-state
AD5390/AD5391/AD5392
CONTROL REGISTER WRITE
Table 25 shows the control register contents for the AD5390 and the AD5392. Table 26 provides bit descriptions. Note that REG1 = REG0 = 0,
A3 to A0 = 1100, and DB13 to DB0 contain the control register data.
Table 25. AD5390/AD5392 Control Register Contents
MSB
CR13
CR12
CR11
CR10
CR9
CR8
CR7
CR6
CR5
CR4
CR3
CR2
CR1
LSB
CR0
Table 26. AD5390 and AD5392 Bit Descriptions
Bit
CR13
CR12
CR11
CR10
CR9
CR8
CR7 to CR4
CR3 to CR2
CR1 to CR0
Description
Power-Down Status. This bit is used to configure the output amplifier state in power–down mode.
CR13 = 1: Amplifier output is high impedance (default on power-up).
CR13 = 0: Amplifier output is 100 kΩ to ground.
REF Select. This bit selects the operating internal reference for the AD539x. CR12 is programmed as follows:
CR12 = 1: Internal reference is 2.5 V (AD5390-2/AD5392-5 default). Recommended operating reference for AD539x-5.
CR12 = 0: Internal reference is 1.25 V (AD5390-3/AD5392-3 default). Recommended operating reference for AD5390-3 and
AD5392-3.
Current Boost Control. This bit is used to boost the current in the output amplifier, thus altering its slew rate and is
configured as follows:
CR11 = 1: Boost mode on. This maximizes the bias current in the output amplifier, optimizing its slew rate but increasing
the power dissipation.
CR11 = 0: Boost mode off (default on power-up). This reduces the bias current in the output amplifier and reduces the
overall power consumption.
Internal/External Reference. This bit determines if the DAC uses its internal reference or an external reference.
CR10 = 1: Internal reference enabled. Reference output depends on data loaded to CR12.
CR10 = 0: External reference selected (default on power-up).
Channel Monitor Enable (see Table 23).
CR9 = 1: Monitor enabled. This enables the channel monitor function. Following a write to the monitor channel in the SFR
register, the selected channel output is routed to the MON_OUT pin.
CR9 = 0: Monitor disabled (default on power-up). When monitor is disabled, the MON_OUT pin is three-stated.
Thermal Monitor Function. When enabled, this function is used to monitor the internal die temperature of the
AD5390/AD5392. The thermal monitor powers down the output amplifiers when the temperature exceeds 130°C. This
function can be used to protect the device when the power dissipation of the device may be exceeded, if a number of
output channels are simultaneously short circuited. A soft power-up re-enables the output amplifiers if the die
temperature has dropped below 130°C.
CR8 = 1: Thermal monitor enabled.
CR8 = 0: Thermal monitor disabled (default on power-up).
Don’t Care.
Toggle Function Enable. This function lets the user toggle the output between two codes loaded to the A and B register
for each DAC. Control Register Bits CR3 and CR2 are used to enable individual groups of eight channels for operation in
toggle mode on the AD5390 and AD5392, as follows:
CR3
Group 1 Channel 8 to Channel 15
CR2
Group 0 Channel 0 to Channel 7
CR2 is the only active bit on the AD5392. Logic 1 written to any bit enables a group of channels and Logic 0 disables a
group. LDAC is used to toggle between the two registers.
Don’t Care.
Rev. C | Page 32 of 40
AD5390/AD5391/AD5392
Table 27 shows the control register contents of the AD5391. Table 28 provides bit descriptions. Note that REG1 = REG0 = 0,
A3 to A0 = 1100, and DB13 to DB0 contain the control register data.
Table 27. AD5391 Control Register Contents
MSB
CR11
CR10
CR9
CR8
CR7
CR6
CR5
CR4
CR3
CR2
CR1
LSB
CR0
Table 28. AD5391 Bit Descriptions
Bit
CR11
CR10
CR9
CR8
CR7
CR6
CR5 to CR2
CR1 to CR0
Description
Power-Down Status. This bit is used to configure the output amplifier state in power-down mode.
CR11 = 1: Amplifier output is high impedance (default on power-up).
CR11 = 0: Amplifier output is 100 kΩ to ground.
REF Select. This bit selects the operating internal reference for the AD5391. CR10 is programmed as follows:
CR10 = 1: Internal reference is 2.5 V (AD5391-5 default). Recommended operating reference for AD5391-5.
CR10 = 0: Internal reference is 1.25 V (AD5391-3 default). Recommended operating reference for AD5391-3.
Current Boost Control. This bit is used to boost the current in the output amplifier, thus altering its slew rate. This bit is
configured as follows:
CR9 = 1: Boost mode on. This maximizes the bias current in the output amplifier, optimizing its slew rate but increasing
the power dissipation.
CR9 = 0: Boost mode off (default on power-up). This reduces the bias current in the output amplifier and reduces the overall
power consumption.
Internal/External Reference. This bits determines if the DAC uses its internal reference or an external reference.
CR8 = 1: Internal reference enabled. Reference output depends on data loaded to CR10.
CR8 = 0: External reference selected (default on power-up).
Channel Monitor Enable (see Table 24).
CR7 = 1: Monitor enabled. This enables the channel monitor function. Following a write to the monitor channel in
the SFR register, the selected channel output is routed to the MON_OUT pin.
CR7 = 0: Monitor disabled (default on power-up). When monitor is disabled, the MON_OUT pin is three-stated.
Thermal Monitor Function. When enabled, this function is used to monitor the internal die temperature of the AD5391,
when enabled. The thermal monitor powers down the output amplifiers when the temperature exceeds 130°C. This function
can be used to protect the device in cases where the power dissipation of the device may be exceeded, if a number of
output channels are simultaneously short circuited. A soft power-up re-enables the output amplifiers if the die temperature
has dropped below 130°C.
CR6 = 1: Thermal monitor enabled.
CR6 = 0: Thermal monitor disabled (default on power-up).
Don’t Care.
Toggle Function Enable. This function lets the user toggle the output between two codes loaded to the A and B register for
each DAC. Control Register Bit CR1 and Bit CR0 are used to enable individual groups of eight channels for operation in
toggle mode on the AD5391, as follows:
CR1
Group 1 Channel 8 to Channel 15
CR0
Group 0 Channel 0 to Channel 7
Logic 1 written to any bit enables a group of channels and Logic 0 disables a group. LDAC is used to toggle between the two
registers.
Rev. C | Page 33 of 40
AD5390/AD5391/AD5392
HARDWARE FUNCTIONS
RESET FUNCTION
POWER-ON RESET
Bringing the RESET line low resets the contents of all internal
registers to their power-on reset state. RESET is a negative edgesensitive input. The default corresponds to m at full scale and
c at zero scale. The contents of all DAC registers are cleared by
setting the outputs to 0 V. This sequence takes 270 μs maximum.
The falling edge of RESET initiates the reset process. BUSY goes
low for the duration, returning high when RESET is complete.
While BUSY is low, all interfaces are disabled and all LDAC
pulses are ignored. When BUSY returns high, the part resumes
normal operation, and the status of the RESET pin is ignored
until the next falling edge is detected.
The AD539x products contain a power-on reset generator
and state machine. The power-on reset resets all registers to a
predefined state, and the analog outputs are configured as high
impedance outputs. The BUSY pin goes low during the poweron reset sequence, preventing data writes to the device.
CLR is negative-edge-triggered and BUSY goes low for the
duration of the CLR execution. Bringing the CLR line low
clears the contents of the DAC registers to the data contained in
the user-configurable CLR register and sets the analog outputs
accordingly. This function can be used in system calibration
to load zero scale and full scale to all channels together. The
execution time for a CLR is 20 μs on the AD5390/AD5391 and
15 μs on the AD5392.
BUSY AND LDAC FUNCTIONS
BUSY is a digital CMOS output indicating the status of the
AD539x devices. BUSY goes low during internal calculations
of x2 data. If LDAC is taken low while BUSY is low, this event
is stored. The user can hold the LDAC input permanently low
and, in this case, the DAC outputs update immediately after
BUSY goes high. BUSY also goes low during a power-on reset
and when a falling edge is detected on the RESET pin. During
this time, all interfaces are disabled and any events on LDAC
are ignored.
The AD539x products contain a global power-down feature that
puts all channels into a low power mode, reducing the analog
power consumption to 1 μA maximum and the digital power
consumption to 20 μA maximum. In power-down mode, the
output amplifier can be configured as a high impedance output
or to provide a 100 kΩ load to ground. The contents of all
internal registers are retained in power-down mode. When
exiting power-down, the settling time of the amplifier elapses
before the outputs settle to their correct value.
MICROPROCESSOR INTERFACING
AD539x to MC68HC11
The serial peripheral interface (SPI) on the MC68HC11 is
configured for master mode (MSTR = 1), clock polarity bit
(CPOL) = 0, and the clock phase bit (CPHA) = 1. The SPI is
configured by writing to the SPI control register (SPCR)—see
the 68HC11 User Manual. SCK of the MC68HC11 drives the
SCLK of the AD539x, the MOSI output drives the serial data
line (DIN) of the AD539x, and the MISO input is driven from
DOUT. The SYNC signal is derived from a port line (PC7). When
data is being transmitted to the AD539x, the SYNC line is taken
low (PC7). Data appearing on the MOSI output is valid on the
falling edge of SCK. Serial data from the MC8HC11 is transmitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle.
The AD539x products contain an extra feature whereby a DAC
register is not updated unless its x2 register has been written
to since the last time LDAC was brought low. Normally, when
LDAC is brought low, the DAC registers are filled with the
contents of the x2 registers. However, these devices update the
DAC register only if the x2 data has changed, thereby removing
unnecessary digital crosstalk.
MC68HC11
DVDD
AD539x
RESET
MISO
SDO
MOSI
DIN
SCK
SCLK
PC7
SYNC
SPI/I2C
Figure 37. AD539x-MC68HC11 Interface
Rev. C | Page 34 of 40
03773-026
ASYNCHRONOUS CLEAR FUNCTION
POWER-DOWN
AD5390/AD5391/AD5392
DVDD
AD539x to PIC16C6x/7x
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit = 0. This is done
by writing to the synchronous serial port control register
(SSPCON)—see the PIC16/17 Microcontroller User Manual.
In Figure 38, I/O port RA1 is used to pulse SYNC and enable
the serial port of the AD539x. This microcontroller transfers
only eight bits of data during each serial transfer operation;
therefore, three consecutive read/write operations are needed,
depending on the mode. Figure 38 shows the connection
diagram.
RESET
SPI/I2C
DVDD
SDO
RxD
TxD
SCLK
P1.1
SYNC
03773-028
DIN
Figure 39. AD539x to 8051 Interface
AD539x
PIC16C6x/7x
AD539x to ADSP2101/ADSP2103
RESET
Figure 40 shows a serial interface between the AD539x and
the ADSP2101/ADSP2103. The ADSP2101/ADSP2103 should
be set up to operate in the SPORT transmit alternate framing
mode. The ADSP2101/ADSP2103 SPORT is programmed
through the SPORT control register and should be configured
as follows: internal clock operation, active low framing, and
16-bit word length. Transmission is initiated by writing a word
to the Tx register after the SPORT has been enabled.
SDI/RC4
SDO
SDO/RC5
DIN
SCK/RC3
SCLK
RA1
SYNC
03773-027
SPI/I2C
Figure 38. AD539x to PIC16C6x/7x Interface
DVDD
AD539x to 8051
The AD539x requires a clock synchronized to the serial data.
The 8051 serial interface must, therefore, be operated in Mode 0.
In this mode, serial data enters and exits through RxD and a
shift clock is output on TxD. Figure 39 shows how the 8051 is
connected to the AD539x. Because the AD539x shifts data out
on the rising edge of the shift clock and latches data in on the
falling edge, the shift clock must be inverted. The AD539x
requires its data with the MSB first. Because the 8051 outputs
the LSB first, the transmit routine must take this into account.
AD539x
ADSP2101/
ADSP2103
RESET
SPI/I2C
DR
SDO
DT
DIN
SCK
SCLK
TFS
RFS
SYNC
03773-029
DVDD
8xC51
AD539x
Figure 40. AD539x to ADSP2101/ADSP2103 Interface
Rev. C | Page 35 of 40
AD5390/AD5391/AD5392
APPLICATION INFORMATION
In any circuit where accuracy is important, careful
consideration of the power supply and ground return layout
helps to ensure the rated performance. The printed circuit
board on which the AD539x is mounted should be designed so
that the analog and digital sections are separated and confined
to certain areas of the board. If the AD539x is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
For supplies with multiple pins (AVDD, AVCC), it is recommended to tie those pins together. The AD539x should have
ample supply bypassing of 10 μF in parallel with 0.1 μF on each
supply located as close to the package as possible—ideally right
up against the device. The 10 μF capacitors are the tantalum
bead type. The 0.1 μF capacitor should have low effective series
resistance (ESR) and effective series inductance (ESI), such as
the common ceramic types that provide a low impedance path
to ground at high frequencies, to handle transient currents due
to internal logic switching.
The power supply lines of the AD539x should use as large a
trace as possible to provide low impedance paths and reduce
the effects of glitches on the power supply line. Fast switching
signals such as clocks should be shielded with digital ground
to avoid radiating noise to other parts of the board, and should
never run near the reference inputs. A ground line routed
between the DIN and SCLK lines helps reduce crosstalk
between them (not required on a multilayer board, because
there is a separate ground plane, but separating the lines helps).
Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feedthrough through the
board. A micro-strip technique is by far the best, but not always
possible with a double-sided board. In this technique, the
component side of the board is dedicated to ground plane,
while signal traces are placed on the soldered side.
Suitable external references for the AD539x-3 include the
ADR280 1.2 V reference. The reference should be decoupled at
the REFOUT/ REFIN pin of the device with a 0.1 μF capacitor.
AVDD
DVDD
0.1µF
10µF
ADR431/
ADR421
0.1µF
AVDD
DVDD
REFOUT/REFIN
0.1µF
REF_GND
VOUT 0
AD539x
VOUT 15
DAC_GND SIGNAL_GND
AGND
DGND
03773-061
POWER SUPPLY DECOUPLING
Figure 41. Typical Configuration with External Reference
Figure 42 shows a typical configuration when using the internal
reference. On power-up, the AD539x defaults to an external
reference; therefore, the internal reference needs to be configured
and turned on via a write to the AD539x control register. On the
AD5390/AD5392, Control Register Bit CR12 lets the user choose
the reference voltage; Bit CR10 is used to select the internal
reference. It is recommended to use the 2.5 V reference when
AVDD = 5 V, and the 1.25 V reference when AVDD = 3 V. On the
AD5391, Control Register Bit CR10 lets the user choose the reference voltage; Bit CR8 is used to select the internal reference.
AVDD
DVDD
0.1µF
10µF
0.1µF
AVDD
DVDD
REFOUT/REFIN
0.1µF
REF_GND
TYPICAL CONFIGURATION CIRCUIT
VOUT 0
AD539x
VOUT 15
DAC_GND SIGNAL_GND AGND DGND
03773-060
Figure 41 shows a typical configuration for the AD539x when
configured for use with an external reference. In the circuit
shown, all AGND, SIGNAL_GND, and DAC_GND pins are
tied together to a common AGND. AGND and DGND are
connected together at the AD539x device. On power-up,
the AD539x defaults to external reference operation. All
AVDD lines are connected together and driven from the same
5 V source. It is recommended to decouple close to the device
with a 0.1 μF ceramic and a 10 μF tantalum capacitor. In this
application, the reference for the AD539x-5 is provided
externally from either an ADR421 or ADR431 2.5 V reference.
Figure 42. Typical Configuration with Internal Reference.
(Digital Connections Omitted for Clarity)
The AD539x contains an internal power-on reset circuit with a
10 ms brown-out time. If the power supply ramp rate exceeds
10 ms, the user should reset the AD539x as part of the initialization process to ensure the calibration data is loaded correctly
into the device.
Rev. C | Page 36 of 40
AD5390/AD5391/AD5392
AD539x MONITOR FUNCTION
The AD5390 contains a channel monitor function consisting
of a multiplexer addressed via the interface, allowing any
channel output to be routed to this pin for monitoring using
an external ADC. The channel monitor function must be
enabled in the control register before any channels are routed
to the MON_OUT pin.
Table 23 and Table 24 contain the decoding information
required to route any channel on the AD5390, AD5391, and
AD5392 to the MON_OUT pin. Selecting Channel Address 63
three-states the MON_OUT pin. The AD539x family also
contains two monitor input pins called MON_IN 1 and
MON_IN 2. The user can connect external signals to these
pins, which under software control can be multiplexed to
MON_OUT for monitoring purposes. Figure 43 shows a typical
monitoring circuit implemented using a 12-bit SAR ADC in a
6-lead SOT package. The external reference input is connected
to MON_IN 1 to allow it to be easily monitored. The controller
output port selects the channel to be monitored, and the input
port reads the converted data from the ADC.
AVDD
REFOUT/REFIN
AD5390
DIN
SYNC
SCLK
Apply LDAC.
The LDAC is used to switch between the A and B registers in
determining the analog output. The first LDAC configures the
output to reflect the data in the A registers. This mode offers
significant advantages if the user wants to generate a square
wave at the output on all channels, as could be required to drive
a liquid-crystal-based, variable optical attenuator.
Configuring the AD5390, for example, the user writes to the
control register and sets CR3 = 1 and CR2 = 1, enabling the two
groups of eight for toggle mode operation. The user must then
load data to all 16 A registers and B registers. Toggling the LDAC
sets the output values to reflect the data in the A and B registers,
and the frequency of the LDAC determines the frequency of the
square wave output. The first LDAC loads the contents of the A
registers to the DAC registers. Toggle mode is disabled via the
control register; the first LDAC following the disabling of the
toggle mode updates the outputs with the data contained in the
A registers.
DATA
REGISTER
A
OUTPUT PORT
DAC
REGISTER
AD7476 CS
MON_OUT
VIN
GND
SCLK
SDATA
AGND
INPUT PORT
INPUT
DATA
CONTROLLER
The toggle mode function allows an output signal to be
generated using the LDAC control signal that switches between
two DAC data registers. This function is configured using the
SFR control register, as follows: A write with REG1 = REG0 = 0,
A3 to A0 = 1100 specifies a control register write. The toggle
mode function is enabled in groups of eight channels using Bit
CR3 and Bit CR2 in the AD5390/AD5392 control register and
using Bit CR1 and Bit CR0 in the AD5391 control register. (See
the Control Register Write section.) Figure 44 shows a block
diagram of the toggle mode implementation. Each DAC
channel on the AD539x contains an A and a B data register.
Note that the B registers can be loaded only when toggle mode
is enabled.
To configure the AD539x for toggle mode of operation, the
sequence of events is as follows:
Enable toggle mode for the required channels via the
control register.
Load data to all A registers.
LDAC
CONTROL INPUT
Figure 44. Toggle Mode Function
THERMAL MONITOR FUNCTION
TOGGLE MODE FUNCTION
2.
VOUT
DATA
REGISTER
B
A/B
Figure 43. Typical Channel Monitoring Circuit
1.
INPUT
REGISTER
14-BIT DAC
DAC_GND SIGNAL_GND
03773-030
VOUT 15
4.
AVDD
MON_IN1
VOUT 0
Load data to all B registers.
03773-031
AD780/
ADR431
3.
The AD539x family has a temperature shutdown function to
protect the chip in case multiple outputs are shorted. The shortcircuit current of each output amplifier is typically 40 mA.
Operating the AD539x at 5 V leads to a power dissipation of
200 mW/shorted amplifier. With five channels shorted, this
leads to an extra watt of power dissipation. For the 52-lead
LQFP, the θJA is typically 44°C/W.
The thermal monitor is enabled by the user using CR8 in the
AD5390/AD5392 control register and CR6 in the AD5391
control register. The output amplifiers on the AD539x are
automatically powered down if the die temperature exceeds
approximately 130°C. After a thermal shutdown has occurred,
the user can re-enable the part by executing a soft power-up if
the temperature has dropped below 130°C or by turning off the
thermal monitor function via the control register.
Power Amplifier Control
Multistage power amplifier designs require a large number of
setpoints in the operation and control of the output stage. The
AD539x are ideal for these applications because of their small
size (LFCSP) and the integration of 8 and 16 channels, offering
Rev. C | Page 37 of 40
AD5390/AD5391/AD5392
12- and 14-bit resolution. Figure 45 shows a typical transmitter
architecture, in which the AD539x DACs can be used in the
following control circuits: IBIAS control, average power control
(APC), peak power control (PPC), transmit gain control (TGC),
and audio level control (ALC). DACs are also required for
variable voltage attenuators, phase shifter control, and dcsetpoint control in the overall amplifier design.
2.5V
REFERENCE
4R
2R
±10V
RANGE
R
1/4 OP747/
1/4 OP4177
4R
VOUT 3
R
R
AD539x-5
2R
0V TO 5V
RANGE
IBIAS
VOUT 4
1/4 OP747/
1/4 OP4177
POWER
AMPLIFIER
I SINK
VOUT 2
R
1/4 OP747/
1/4 OP4177
EXCITER
1/4 OP747/
1/4 OP4177
VOUT 1
0V TO 10V
RANGE
R
AUDIO
SOURCE
±5V
RANGE
R
VOUT 0
50Ω
LOAD
R1
03773-033
PHASE
SHIFT
0.1µF
Figure 46. Output Configurations for Process Control Applications
ALC
PPC
APC
TGC
03773-032
Optical Transceivers
Figure 45. Multistage Power Amplifier Control
Process Control Applications
The AD539x-5 family is ideal for process control applications
because it offers a combination of 8 and 16 channels and 12-bit
and 14-bit resolution. These applications generally require
output voltage ranges of 0 V to 5 V ± 5 V, 0 V to 10 V ± 10 V,
and current sink and source functions. The AD539x-5 products
operate from a single 5 V supply and, therefore, require external
signal conditioning to achieve the output ranges described here.
Figure 46 shows configurations to achieve these output ranges.
The key advantages of using AD539x-5 products in these
applications are small package size, pin compatibility with the
ability to upgrade from 12 to 14 bits, integrated on-chip 2.5 V
reference with 10 ppm/°C maximum temperature coefficient,
and excellent accuracy specifications. The AD539x-5 family
contains an offset and gain register for each channel, so users
can perform system-level calibration on a per-channel basis.
The AD539x-3 family of products are ideally suited to optical
transceiver applications. In 300-pin MSA applications, for
example, digital-to-analog converters are required to control the
laser power, APD bias, and modulator amplitude. Diagnostic
information is required as analog outputs from the module. The
AD539x-3 products offer a combination of 8/16 channels, a
resolution of 12/14 bits in a 64-lead LFCSP, and operate from a
supply voltage of 2.7 V to 5.5 V supply with internal reference.
The AD539x-3 parts also feature I2C-compatible and SPI interfaces, making them ideal components for use in these applications.
Figure 47 shows a typical configuration in an optical transceiver
application.
3V
CONTROLLER
SDA
SCL
I 2C
BUS
PIN/APD
AND TIA
AVDD
SCL
REFOUT/REFIN
IRXP
VLSRBIAS
VLSRPWRMON
VXLOPMON
AVDD
REFIN
IMODMON
10G LDD
AND
LASER
DVDD
SDA
AIN
MUX
IMPD
IBIASMON
12-BIT
ADC
AD539x-3
IBIAS
IMOD
AD7994
03773-062
TIAs
Figure 47. Optical Transceiver using the AD539x-3
Rev. C | Page 38 of 40
AD5390/AD5391/AD5392
OUTLINE DIMENSIONS
0.60 MAX
9.00
BSC SQ
0.60
MAX
64 1
49
48
PIN 1
INDICATOR
PIN 1
INDICATOR
0.50
BSC
8.75
BSC SQ
0.50
0.40
0.30
16
17
33
32
0.80 MAX
0.65 TYP
12° MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.05 MAX
0.02 NOM
0.30
0.23
0.18
SEATING
PLANE
0.25 MIN
7.50
REF
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
Figure 48. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm x 9 mm Body, Very Thin Quad
(CP-64-3)
Dimensions shown in millimeters
0.75
0.60
0.45
12.20
12.00 SQ
11.80
1.60
MAX
52
40
39
1
PIN 1
10.20
10.00 SQ
9.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.15
0.05
SEATING
PLANE
VIEW A
0.20
0.09
7°
3.5°
0°
0.10
COPLANARITY
13
27
14
VIEW A
0.65
BSC
LEAD PITCH
26
0.38
0.32
0.22
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BCC
Figure 49. 52-Lead Low Profile Quad Flat Package [LQFP]
(ST-52)
Dimensions shown in millimeters
Rev. C | Page 39 of 40
051706-A
1.00
0.85
0.80
7.25
7.10 SQ
6.95
EXPOSED PAD
(BOTTOM VIEW)
080108-C
TOP VIEW
AD5390/AD5391/AD5392
ORDERING GUIDE
Temperature
Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Resolution
14-bit
14-bit
14-bit
14-bit
14-bit
14-bit
14-bit
14-bit
14-bit
14-bit
14-bit
14-bit
AVDD
2.7 V to 3.6 V
2.7 V to 3.6 V
2.7 V to 3.6 V
2.7 V to 3.6 V
2.7 V to 3.6 V
2.7 V to 3.6 V
4.5 V to 5.5 V
4.5 V to 5.5 V
4.5 V to 5.5 V
4.5 V to 5.5 V
4.5 V to 5.5 V
4.5 V to 5.5 V
Output
Channels
16
16
16
16
16
16
16
16
16
16
16
16
Linearity
Error (LSBs)
±4
±4
±4
±4
±4
±4
±3
±3
±3
±3
±3
±3
Package
Description
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
Package
Option
CP-64-3
CP-64-3
CP-64-3
CP-64-3
CP-64-3
CP-64-3
CP-64-3
CP-64-3
CP-64-3
CP-64-3
CP-64-3
CP-64-3
−40°C to +85°C
−40°C to +85°C
14-bit
14-bit
2.7 V to 3.6 V
4.5 V to 5.5 V
16
16
±4
±3
52-Lead LQFP
52-Lead LQFP
ST-52
ST-52
AD5391BCP-3
AD5391BCP-3-REEL
AD5391BCP-3-REEL7
AD5391BCPZ-31
AD5391BCP-5
AD5391BCP-5-REEL
AD5391BCP-5-REEL7
AD5391BCPZ-51
AD5391BCPZ-5-REEL1
AD5391BCPZ-5-REEL71
AD5391BSTZ-31
AD5391BSTZ-51
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
12-bit
12-bit
12-bit
12-bit
12-bit
12-bit
12-bit
12-bit
12-bit
12-bit
12-bit
12-bit
2.7 V to 3.6 V
2.7 V to 3.6 V
2.7 V to 3.6 V
2.7 V to 3.6 V
4.5 V to 5.5 V
4.5 V to 5.5 V
4.5 V to 5.5 V
4.5 V to 5.5 V
4.5 V to 5.5 V
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
16
16
16
16
16
16
16
16
16
16
16
16
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
52-Lead LQFP
52-Lead LQFP
CP-64-3
CP-64-3
CP-64-3
CP-64-3
CP-64-3
CP-64-3
CP-64-3
CP-64-3
CP-64-3
CP-64-3
ST-52
ST-52
AD5392BCP-3
AD5392BCP-3-REEL
AD5392BCP-3-REEL7
AD5392BCPZ-31
AD5392BCP-5
AD5392BCP-5-REEL
AD5392BCP-5-REEL7
AD5392BCPZ-51
AD5392BSTZ-31
AD5392BSTZ-51
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
14-bit
14-bit
14-bit
14-bit
14-bit
14-bit
14-bit
14-bit
14-bit
14-bit
2.7 V to 3.6 V
2.7 V to 3.6 V
2.7 V to 3.6 V
2.7 V to 3.6 V
4.5 V to 5.5 V
4.5 V to 5.5 V
4.5 V to 5.5 V
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
8
8
8
8
8
8
8
8
8
8
±4
±4
±4
±4
±3
±3
±3
±3
±4
±3
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
52-Lead LQFP
52-Lead LQFP
CP-64-3
CP-64-3
CP-64-3
CP-64-3
CP-64-3
CP-64-3
CP-64-3
CP-64-3
ST-52
ST-52
Model
AD5390BCP-3
AD5390BCP-3-REEL
AD5390BCP-3-REEL7
AD5390BCPZ-3 1
AD5390BCPZ-3-REEL1
AD5390BCPZ-3-REEL71
AD5390BCP-5
AD5390BCP-5-REEL
AD5390BCP-5-REEL7
AD5390BCPZ-51
AD5390BCPZ-5-REEL1
AD5390BCPZ-5-REEL71
AD5390BSTZ-31
AD5390BSTZ-51
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
EVAL–AD5390EBZ1
EVAL–AD5391EBZ1
EVAL–AD5392EBZ1
1
Evaluation Board
Evaluation Board
Evaluation Board
Z = RoHS Compliant Part.
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03773-0-1/09(C)
Rev. C | Page 40 of 40
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